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Digilent Genesys 2, Справочное руководство

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Digilent Genesys 2 Скачать руководство пользователя страница 13

For the FPGA to be able to configure itself from the SPI Flash, it first needs to be programmed with the bitstream. This is 
called indirect programming and is a two-step process controlled by Hardware Manager (Vivado) or iMPACT (ISE). First, the 
FPGA is programmed with a design that can program flash devices, and then data is transferred to the flash device via the 
FPGA circuit (this complexity is hidden from the user by the Xilinx tools). After the flash device has been programmed, it can 
automatically configure the FPGA at a subsequent power-on or reset event as determined by the mode jumper setting. 
Programming files stored in the flash device will remain until they are overwritten, regardless of power-cycle events. 

Programming the flash can take as long as four to five minutes, which is mostly due to the lengthy erase process inherent to the 
memory technology. Once written however, FPGA configuration can be very fast, less than a second. Bitstream compression, 
SPI bus width, and configuration rate are factors controlled by the Xilinx tools that can affect configuration speed. The on-
board flash has a Quad-SPI interface, which supports single (x1), dual (x2) and quad (x4) modes. The quad mode results in the 
fastest possible data transfer rate. For it to work, the bitstream needs to be generated with the x4 bus width option (Vivado 
device property) and the non-volatile quad configuration bit in the flash to be enabled. The Genesys 2 is shipped with this bit 
enabled. 

Indirect programming of the flash can be done using the iMPACT tool included with ISE or Hardware Manager of Vivado. 
The correct part to be set in the tools is s25fl256xxxxxx0 from the manufacturer Spansion. 

You can program the FPGA from a pen drive attached to the USB-Host port (J7-top row) or a microSD card inserted into J3 
by doing the following: 

1. Format the storage device (pen drive or microSD card) with a FAT32 file system.
2. Place a single .bit configuration file in the root directory of the storage device.
3. Attach the storage device to the Genesys 2.
4. Set the JP5 Programming Mode jumper on the Genesys 2 to “USB/SD”.
5. Select the desired storage device using JP4.
6. Push the PROG button or power-cycle the Genesys 2.

The FPGA will automatically configure with the .bit file on the selected storage device. Any .bit files that are not built for the 
proper Kintex-7 device will be rejected by the FPGA. The Auxiliary Function Status or “BUSY” LED () (LD11) gives visual 
feedback on the state of the configuration process when the FPGA is not yet programmed: 

• When steadily lit the auxiliary microcontroller is either booting up or currently reading the configuration medium 

(microSD or pen drive) and downloading a bitstream to the FPGA.

• A slow pulse means the microcontroller is waiting for a configuration medium to be plugged in.
• In case of an error during configuration the LED () will blink rapidly. It could be that the device plugged in is not 

getting recognized, it is not properly formatted or the bitstream is not compatible with the FPGA.

When the FPGA is has been successfully configured, the behavior of the LED () is application-specific. For example, if a USB 
keyboard or mouse is plugged in, a rapid short blink will signal the receipt of an HID input report from peripheral. 

The Genesys 2 board contains two external memories: a 1GiByte volatile DDR3 memory and a 32MiByte non-volatile serial 
Flash device. The DDR3 uses two 16-bit wide memory component with industry-standard interface soldered on the board 
resulting in a 32-bit data bus. The serial Flash is on a dedicated quad-mode (x4) SPI bus. 

The Genesys 2 includes two Micron MT41J256M16HA-107 DDR3 memory component creating a single rank, 32-bit wide 
interface. It is routed to a 1.5V-powered HP (High Performance) FPGA bank with 40 ohm controlled single-ended trace 
impedance. For data signals 40 ohm DCI terminations in the FPGA are used to match the trace characteristics. Similarly, on 
the memory side on-die terminations (ODT) are used for impedance matching. Address/Control signals are terminated using 
discrete resistors. 

The highest data rate supported is 1800Mbps. 

5.3. USB Host and Micro SD Programming

6. Memory

6.1. DDR3

Page 13 of 35

Содержание Genesys 2

Страница 1: ...x part number XC7K325T 2FFG900C fast external memories high speed digital video ports and wide expansions options make the Genesys 2 well suited for data and video processing applications Several buil...

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Страница 5: ...to 10 3125Gbps gigabit transceivers 1800Mbps DDR3 data rate with 32 bit data width Commercial 2 speed grade Fully bonded 400 pin FMC HPC connector USB UART Bridge 8 user switches 6 buttons OLED VGA c...

Страница 6: ...e Vivado Design Suite as well as the ISE toolset Included in the box is a voucher that unlocks the Design Edition of Vivado that is device locked to the Genesys 2 This allows designs to be implemented...

Страница 7: ...nnector 21 VGA connector 22 HDMI source connector 23 FPGA configuration source jumper 24 HDMI sink connector 25 Power switch 26 Power jack 12VDC Table 1 Genesys 2 features and connectors The Genesys 2...

Страница 8: ...s 60 C and stops when it drops back to 40 C To develop new FPGA designs for the Genesys 2 download and install the Xilinx Vivado Design Suite http www xilinx com products design tools vivado html The...

Страница 9: ...USB FMC Clocks Pmod Ethernet SD slot Flash DisplayPort HDMI IC42 LTC3855 1 6 A 0 8 A 1 0 V FPGA Core IC30 LTC3866 14 A 1 2 A 1 8 V FPGA Auxiliary IC36 LTC3605 5 A 1 6 A 1 5 V DDR3 and FPGA I O IC32 LT...

Страница 10: ...Power monitoring circuit parameters The configuration and calibration registers are volatile so they need to be initialized after power up After initialization is done voltage current and power value...

Страница 11: ...actual usage the fan might not be needed at all In this case the enable signal can be used to stop the fan and start it when the FPGA internal temperature as read by the XADC gets above a certain lim...

Страница 12: ...SB mass storage device configuration modes already operate at their maximum possible speed After being successfully programmed the FPGA will cause the DONE LED LD14 to illuminate Pressing the PROG but...

Страница 13: ...e 3 Attach the storage device to the Genesys 2 4 Set the JP5 Programming Mode jumper on the Genesys 2 to USB SD 5 Select the desired storage device using JP4 6 Push the PROG button or power cycle the...

Страница 14: ...atio 4 1 VCCAUX_IO 2 0V Memory type Components Memory part MT41J256M16XX 107 Memory voltage 1 5V Data width 32 Data mask Enabled Input clock period 5004ps 200MHz Output driver impedance RZQ 7 Chip Sel...

Страница 15: ...board includes a Realtek RTL8211E VL PHY paired with an RJ 45 Ethernet jack with integrated magnetics to implement a 10 100 1000 Ethernet port for network connection The PHY interfaces with the FPGA...

Страница 16: ...nnected to MRCC GPIO pins AD12 AD11 in bank 33 This input clock can drive MMCMs or PLLs to generate clocks of various frequencies and with known phase relationships that may be needed throughout a des...

Страница 17: ...FT232R and the FPGA are shown in Figure 8 The Genesys 2 provides two interface types that can be used to transfer user data between a PC and an FPGA design Both of the interfaces have a software comp...

Страница 18: ...y the USB controller read transfer When high the bus is driven by the FPGA write transfer CLKO Input 60 MHz clock used in synchronous mode Data is launched and can be captured on the rising edge Table...

Страница 19: ...are organized differently and the keyboard interface allows bi directional data transfers so the host device can illuminate state LEDs on the keyboard Bus timings are shown in Figure 11 The clock and...

Страница 20: ...data until the clock is released The keyboard sends data to the host in 11 bit words that contain a 0 start bit followed by 8 bits of scan code LSB first followed by an odd parity bit and terminated w...

Страница 21: ...en the fixed USB roles of the Genesys2 are not enough an on board USB 2 0 transceiver PHY provides physical layer implementation for any USB 2 0 user application It connect to a USB A J7 bottom row an...

Страница 22: ...gned to a pushbutton or slide switch was inadvertently defined as an output The five pushbuttons arranged in a plus sign configuration are momentary switches that normally generate a low output when t...

Страница 23: ...12 pin Pmod connector provides two power pins 6 and 12 two ground pins 5 and 11 and eight logic signals as shown in Figure 20 The VCC and Ground pins of can deliver up to 1A of current per pin Pin ass...

Страница 24: ...JD7 JXADC7 A14 JA8 C17 JB8 R16 JC8 E6 JD8 JXADC8 A16 JA9 D18 JB9 T9 JC9 J2 JD9 JXADC9 B17 JA10 E18 JB10 U11 JC10 G6 JD10 JXADC10 A18 Table 11 Genesys 2 Pmod pin assignments Digilent produces a large c...

Страница 25: ...d future FMC modules The Genesys 2 opens the door to the full range of I O standards supported by the Kintex 7 HR High Range I O architecture over the FMC connector The pin out of the FMC connector ca...

Страница 26: ...3 Quad 116 pinout Quad Primitive Pin type Pin FMC signal 117 GTXE2_ CHANNEL X0Y8 MGTXTXP N0 K2 K1 DP8_C2M_P N MGTXRXP N0 K6 K5 DP8_M2C_P N X0Y9 MGTXTXP N1 J4 J3 DP9_C2M_P N MGTXRXP N1 H6 H5 DP9_M2C_P...

Страница 27: ...5 input Both ports use HDMI type A receptacles and include HDMI buffer TMDS141 The buffers work by terminating equalizing conditioning and forwarding the HDMI stream between the connector and FPGA pin...

Страница 28: ...1 3 http www hdmi org or later specifications for more information DisplayPort is a relatively new industry standard for digital display technology Its advantages over existing technologies are higher...

Страница 29: ...ry channel is a bidirectional LVDS bus Depending on the Xilinx tool IP version instantiating a differential I O buffer with LVDS signaling standard might not be possible The work around is to have two...

Страница 30: ...ires in controller terminology are CS D C SDIN and SCLK but CS is hard wired to ground This adds to the reset and two power control signals for proper start up sequencing The signals are summarized in...

Страница 31: ...VBAT by pulling OLED _VBAT low Wait 100ms for voltage to stabilize 5 Clear screen by writing zero to the display buffer 6 Send Display On command 0xAF Command function Command bytes Charge pump enabl...

Страница 32: ...sizing the right frequency from the on board 100 MHz reference oscillator For proper use the concept of audio paths needs to be understood Internal to the codec there are two signal paths Playback and...

Страница 33: ...eference digilentinc com tag reference do showtag tag reference programmable logic https reference digilentinc com tag programmable logic do showtag tag programmable logic genesys 2 https reference di...

Страница 34: ...https twitter com digilentinc https www facebook com Digilent https www youtube com user DigilentInc https instagram com digilentinc https github com digilent Connect With Us Page 34 of 35...

Страница 35: ...eddit com r digilent https www linkedin com company 1454013 https www flickr com photos 127815101 N07 Page 35 of 35 11 9 2016 https reference digilentinc com reference programmable logic genesys 2 ref...

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