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7/30/2019

Cora Z7 Reference Manual [Reference.Digilentinc]

https://reference.digilentinc.com/reference/programmable-logic/cora-z7/reference-manual?_ga=2.21685883.1349070004.1564406803-1961480359.… 22/23

Product
Name

Variant

Revision

Problem

Status

Cora Z7

All

All

Negative CK-to-DQS delays in the board files are causing critical warnings in Vivado
>2017.4:
[PSU-1] Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative
value -0.050 . PS DDR interfaces might fail when entering negative DQS skew values.

The negative values are due to CK trace being shorter than any of the four DQS traces.

In the early days of Zynq board design negative values where listed as sub-optimal, but not
erroneous. Tree topology instead of fly-by was also among the routing recommendations for
DDR3 layouts. So the Cora Z7 was designed with this sub-optimal layout due to space
constraints. During Write Leveling calibration, 0 is used as an initial value instead of the
negative preset delays. After calibration, if the skew is still too low, the clock is inverted. See
ug585 pg 316 for more details. All Cora Z7 boards shipped to customers are functionally
tested and pass the DDR3 calibration process.

Xilinx recommendations changed in the mean time, both in terms of routing topology and
delay values. A trace of this can be found here:
https://www.xilinx.com/support/answers/53039.html

(https://www.xilinx.com/support/answers/53039.html)

. The > 0ns requirement was introduced

to be in line with non-Zynq MIG-based designs, where negative delays were never
permitted.

To silence the warnings, zero board delays can be set in Processing System configuration.
The calibration algorithm seems to be using zero starting values anyway when negative
delays are given.

will
not fix

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(https://reference.digilentinc.com/tag/doc?do=showtag&tag=doc)

(https://reference.digilentinc.com/tag/cora-z7?do=showtag&tag=cora-z7)

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Содержание Cora Z7

Страница 1: ...nts the ability to surround the processor with a unique set of software defined peripherals and controllers tailored for the target application The Cora Z7 s wide array of hardware interfaces from a 1Gbps Ethernet PHY to analog to digital converters and general purpose input output pins make it an ideal platform for the development of a vast variety of embedded applications The small form factor a...

Страница 2: ...7 30 2019 Cora Z7 Reference Manual Reference Digilentinc https reference digilentinc com reference programmable logic cora z7 reference manual _ga 2 21685883 1349070004 1564406803 1961480359 1 2 23 ...

Страница 3: ... processor FPGA Programmable logic equivalent to Artix 7 FPGA 4 400 Programmable logic slices 3 600 80 DSP slices 60 270 KB of block RAM 225 KB DDR3 memory controller with 8 DMA channels and 4 High Performance AXI3 Slave ports High bandwidth peripheral controllers 1G Ethernet USB 2 0 SDIO Low bandwidth peripheral controllers SPI UART CAN I2C Dual channel 1 MSPS internal analog digital converter Pr...

Страница 4: ...wo Push buttons Two RGB LEDs Expansion Connectors Two Pmod connectors 16 Total FPGA I O Arduino chipKIT Shield connector Up to 49 Total FPGA Digital I O 6 Single ended 0 3 3V Analog inputs to XADC 8 Differential 0 1 0V Analog inputs to XADC Unloaded expansion header 12 additional FPGA Digital I O Z7 07S variant in parentheses where different https reference digilentinc com _detail reference progra...

Страница 5: ...the same capabilities but the 10 has about a 1 2 times larger internal FPGA and an additional processor core as compared to the 07S The differences between the two variants are summarized below Product Variant Cora Z7 10 Cora Z7 07S Zynq Part XC7Z010 1CLG400C XC7Z007S 1CLG400C ARM Processor Cores 2 1 1 MSPS On chip ADC Yes Yes Look up Tables LUTs 17 600 14 400 Flip Flops 35 200 28 800 DSP Slices 8...

Страница 6: ...gilent FPGAs the Cora Z7 cannot be powered through the Shield Header A red power good LED LD7 driven by the 3 3V output VCC3V3 of the DA9062 regulator indicates that the board is receiving power and that the onboard supplies are functioning as expected If this LED does not illuminate when an acceptable power supply is connected please contact your distributor or Digilent Support http forum digilen...

Страница 7: ...nductor DA9062 2 5A 1 8V FPGA Auxiliary USB port Ethernet IC15 Dialog Semiconductor DA9062 1 5A 1 35V FPGA DDR3L memory IC15 Dialog Semiconductor DA9062 2 5A 1 8V FPGA XADC IC15 Dialog Semiconductor DA9062 100mA Table 1 1 Cora Z7 Power Rails With JP3 set to USB The Zynq APSoC is divided into two distinct subsystems The Processing System PS and the Programmable Logic PL Figure 2 1 shows an overview...

Страница 8: ...nnected to MIO pins can instead route their I O through the PL via the Extended MIO EMIO interface The peripheral controllers are connected to the processors as slaves via the AMBA interconnect and contain readable writable control registers that are addressable in the processors memory space The programmable logic is also connected to the interconnect as a slave and designs can implement multiple...

Страница 9: ... 1349070004 1564406803 1961480359 1 9 23 1 N C 2 MODE0 3 MODE1 4 MODE2 5 MODE3 6 MODE4 7 VCFG0 8 VCFG1 9 Ethernet Reset 10 Ethernet Interrupt 11 USB Over Current 12 Shield Reset 13 N C 14 UART Input 15 UART Output MIO 501 1 0V Peripherals Pin ETH 0 USB 0 SDIO 0 16 TXCK 17 TXD0 18 TXD1 19 TXD2 20 TXD3 21 TXCTL 22 RXCK 23 RXD0 24 RXD1 25 RXD2 26 RXD3 27 RXCTL ...

Страница 10: ... cora z7 reference manual _ga 2 21685883 1349070004 1564406803 1961480359 10 23 28 DATA4 29 DIR 30 STP 31 NXT 32 DATA0 33 DATA1 34 DATA2 35 DATA3 36 CLK 37 DATA5 38 DATA6 39 DATA7 40 CCLK 41 CMD 42 D0 43 D1 44 D2 45 D3 46 RESETN 47 CD 48 N C 49 N C 50 N C 51 N C 52 MDC 53 MDIO Table 2 1 MIO Pinout 3 Zynq Configuration ...

Страница 11: ...execution to the FSBL in OCM Stage 1 During this stage the FSBL first finishes configuring the PS components such as the DDR memory controller Then if a bitstream is present in the Zynq Boot Image it is read and used to configure the PL Finally the user application is loaded into memory from the Zynq Boot Image and execution is handed off to it Stage 2 The last stage is the execution of the user a...

Страница 12: ...les are available on the Cora Z7 Resource Center https reference digilentinc com reference programmable logic cora z7 start and automatically configure the Zynq Processing System IP core with the correct parameters For best DDR3L performance DRAM training is enabled for write leveling read gate and read data eye options in the PS Configuration Tool in Xilinx tools Training is done dynamically by t...

Страница 13: ...uides ug585 Zynq 7000 TRM pdf SDIO host mode is the only mode supported Signal Name Description Zynq Pin SD Slot Pin SD_D0 Data 0 MIO42 7 SD_D1 Data 1 MIO43 8 SD_D2 Data 2 MIO44 1 SD_D3 Data 3 MIO45 2 SD_CCLK Clock MIO40 5 SD_CMD Command MIO41 3 SD_CD Card Detect MIO47 9 Table 6 1 microSD pinout The SD slot is powered from the 3 3V rail but is connected through MIO Bank 1 501 1 8V Therefore a TI T...

Страница 14: ...l work just fine without loading C35 Whether the Cora Z7 is configured as an embedded host or a general purpose host it can provide 1A on the 5V VBUS line Note that if your design uses the USB Host port embedded or general purpose then the Cora Z7 should be powered via a wall adapter capable of providing more power The Cora Z7 uses a Realtek RTL8211E VL PHY to implement a 10 100 1000 Ethernet port...

Страница 15: ...n on using the Gigabit Ethernet MAC refer to the Zynq Technical Reference manual http www xilinx com support documentation user_guides ug585 Zynq 7000 TRM pdf The Cora Z7 provides a 50 MHz clock to the Zynq PS_CLK input which is used to generate the clocks for each of the Processing System PS subsystems The 50 MHz input allows the processor to operate at a maximum frequency of 650 MHz and the DDR3...

Страница 16: ...without disturbing the debug environment For example the previous break points set by the user remain valid after system reset Due to security concerns system reset erases all memory content within the PS including the OCM The PL is also cleared during a system reset System reset does not cause the boot mode strapping pins to be re sampled The SRST button also causes the CK_RST signal to toggle an...

Страница 17: ... also greatly expands the potential color palette of the tri color led Individually adjusting the duty cycle of each color between 50 and 0 causes the different colors to be illuminated at different intensities allowing virtually any color to be displayed Pmod connectors are 2 6 right angle 100 mil spaced female connectors that mate with standard 2 6 pin headers Each 12 pin Pmod connector provides...

Страница 18: ...tors the operator must take care to prevent any shorts The Cora Z7 can be connected to standard Arduino and chipKIT shields to add extended functionality Special care was taken while designing the Cora S7 to make sure it is compatible with the majority of Arduino and chipKIT shields on the market The shield connector has 45 pins connected to the FPGA for general purpose Digital I O Due to the flex...

Страница 19: ...XADC ground reference on the FPGA VREFN N C Not Connected Not Connected IOREF Digital I O Voltage reference Connected to the Cora Z7 3 3V Power Rail See the Power Supplies section RST Reset to Shield Connected to the red SRST button and a Digital I O of the FPGA When JP1 is shorted it is also connected to the DTR signal of the FTDI USB UART bridge 3V3 3 3V Power Rail Connected to the Cora Z7 3 3V ...

Страница 20: ...e pins The pins labeled A0 A5 can also be used as digital inputs or outputs as they are also connected directly to the FPGA before the resistor divider circuit also shown in Figure 13 2 1 https reference digilentinc com _media reference programmable logic cora z7 cora analog single ended png Figure 13 2 1 Single Ended Analog Inputs The pins labeled A6 A11 are connected directly to 3 pairs of analo...

Страница 21: ... FPGAs and Zynq 7000 All Programmable SoC XADC Dual 12 Bit 1 MSPS Analog to Digital Converter A demo that uses the XADC core is available through the Cora Z7 Resource Center https reference digilentinc com reference programmable logic cora z7 start The Cora Z7 has an additional 12 Digital I O pins in the form of a 16 pin unloaded expansion header J1 The two outer most pins labeled V of this header...

Страница 22: ... trace of this can be found here https www xilinx com support answers 53039 html https www xilinx com support answers 53039 html The 0ns requirement was introduced to be in line with non Zynq MIG based designs where negative delays were never permitted To silence the warnings zero board delays can be set in Processing System configuration The calibration algorithm seems to be using zero starting v...

Страница 23: ...cora z7 reference manual _ga 2 21685883 1349070004 1564406803 1961480359 23 23 https www facebook com Digilent https www youtube com user DigilentInc https instagram com digilentinc https github com digilent https www reddit com r digilent https www linkedin com company 1454013 https www flickr com photos 127815101 N07 ...

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