7/30/2019
Cora Z7 Reference Manual [Reference.Digilentinc]
https://reference.digilentinc.com/reference/programmable-logic/cora-z7/reference-manual?_ga=2.21685883.1349070004.1564406803-1961480359.… 21/23
Figure 13.2.3. Dedicated Analog Input Pair
The XADC core within the Zynq is a dual channel 12-bit analog-to-digital converter capable of operating at 1 MSPS. Either channel can be
driven by any of the analog inputs connected to the shield pins. The XADC core is controlled and accessed from a user design via either the
Dynamic Reconfiguration Port (DRP) or an AXI interface connected to the Zynq PS. These interfaces also provide access to voltage
monitors that are present on each of the FPGA’s power rails, and a temperature sensor that is internal to the FPGA. For more information
on using the XADC core, refer to the Xilinx document titled “7 Series FPGAs and Zynq-7000 All Programmable SoC XADC Dual 12-Bit 1
MSPS Analog-to-Digital Converter”. A demo that uses the XADC core is available through the Cora Z7 Resource Center
(https://reference.digilentinc.com/reference/programmable-logic/cora-z7/start)
The Cora Z7 has an additional 12 Digital I/O pins in the form of a 16-pin unloaded expansion header (J1). The two outer-most pins
(labeled V) of this header are connected to the Cora Z7's 3.3V rail. The next two outermost pins (labeled G) are connected to ground. The
remaining 12 pins (labeled IO2-IO13) are directly connected to the Zynq PL. Zynq PL pin mappings for the unloaded expansion header can
be found in the Cora Z7 master XDC file, available through the Cora Z7 Resource Center
(https://reference.digilentinc.com/reference/programmable-logic/cora-z7/start)
Figure 14.1. Unloaded Expansion Header
Although we strive to provide perfect products, we are not infallible. The Cora Z7 is subject to the limitations below.
Product
Name
Variant
Revision
Problem
Status
14 Unloaded Expansion Header
Hardware errata
