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22.8.2018

Cmod S7 Reference Manual [Reference.Digilentinc]

https://reference.digilentinc.com/reference/programmable-logic/cmod-s7/reference-manual

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When the Cmod S7 is powered by the USB connector, the voltage from the USB device is driven onto the VU pin. This makes it
possible to power an external circuit from the USB host in addition to the Cmod S7. The VU pin is driven via a schottky diode, so a
small voltage drop will occur, but it should be assumed that the voltage present on VU will be close to 5V.

Warning: When a USB host is attached to the micro USB connector, the VU pin on the DIP headers (pin 24) is driven to the
voltage being provided by the USB host (typically 4.5V-5.5V). To avoid risk of damage, any power source attached to the VU
pin must be disconnected before a USB host is attached. Not taking this precaution can be particularly dangerous if the
power source is a battery.

After power-on, the Spartan-7 FPGA must be configured (or programmed) before it can perform any functions. The FPGA can be
configured in one of two ways:

A PC can use the Digilent USB-JTAG circuitry (port J5) to program the FPGA any time the power is on.
A file stored in the nonvolatile serial (SPI) flash device can be transferred to the FPGA using the SPI port.

Figure 2.1 shows the different options available for configuring the FPGA.

(https://reference.digilentinc.com/_detail/reference/programmable-logic/cmod-s7/cmod-s7-config.png?id=reference%3Aprogrammable-
logic%3Acmod-s7%3Areference-manual)

Figure 2.1 Configuration

The FPGA configuration data is stored in files called bitstreams that have the .bit file extension. The Vivado software from Xilinx can
create bitstreams from VHDL, Verilog®, or block-level designs.

Bitstreams are stored in volatile memory cells within the FPGA. This data defines the FPGA's logic functions and circuit connections,
and it remains valid until it is erased by removing board power, or by writing a new configuration file using the JTAG port.

A Spartan-7 25T bitstream is typically 9,935,224 bits. The time it takes to program the Cmod S7 can be decreased by compressing the
bitstream before programming, and then allowing the FPGA to decompress the bitstream itself during configuration. Depending on
design complexity, compression ratios of 10x can be achieved. Bitstream compression can be enabled within the Xilinx tools to occur
during generation, and is enabled by default in Digilent's master XDC file for the Cmod S7. For more information on how to do this,
consult the Xilinx documentation for the toolset being used.

After successful programming, the FPGA will cause the “DONE” LED () to illuminate.

The following sections provide greater detail about programming the Cmod S7 using the different methods available.

The Xilinx tools typically communicate with FPGAs using the Test Access Port and Boundary-Scan Architecture, commonly referred to
as JTAG. During JTAG programming, a .bit file is transferred from the PC to the FPGA using the onboard Digilent USB-JTAG circuitry
(port J5). JTAG programming can be performed any time after the Cmod S7 has been powered on. If the FPGA is already configured,
then the existing configuration is overwritten with the bitstream being transferred over JTAG.

Programming the Cmod S7 with an uncompressed bitstream using the onboard USB-JTAG circuitry usually takes around 
seconds. JTAG programming can be performed by Vivado's Hardware Manager.

Since the FPGA's memory on the Cmod S7 is volatile, it relies on the Quad-SPI flash memory to store the configuration between power
cycles. This configuration mode is called Master SPI. The blank FPGA takes the role of master and reads the configuration file out of the
flash device upon power-up. To that effect, a configuration file needs to first be written to the flash. When programming a non-volatile
flash device, a bitstream file is transferred to the flash in a two-step process. First, the FPGA is programmed with a circuit that can
program flash devices, and then data is transferred to the flash device via the FPGA circuit (this complexity is hidden from the user by
the Xilinx tools). This is called indirect programming. After the flash device has been programmed, it will automatically configure the
FPGA at any subsequent power-on event. Programming files stored in the flash device will remain until they are overwritten, regardless
of power-cycle events.

Quad-SPI programming can be performed using Vivado's Hardware Manager.

2 FPGA Configuration

2.1 JTAG Configuration

2.2 Quad-SPI Configuration

Содержание Cmod S7

Страница 1: ...s an external power input rail and ground are routed to 100 mil spaced through hole pins making the Cmod S7 well suited for use with solderless breadboards At just 0 7 by 3 05 inches it can be loaded...

Страница 2: ...22 8 2018 Cmod S7 Reference Manual Reference Digilentinc https reference digilentinc com reference programmable logic cmod s7 reference manual 2 12 Xilinx Spartan 7 FPGA XC7S25 1CSGA225C Features...

Страница 3: ...factor header 32 total FPGA I O 2 single ended 0 3 3V analog inputs to XADC 2 power pins https reference digilentinc com _detail reference programmable logic cmod s7 cmod s7 callout png id reference...

Страница 4: ...e 1 1 The characteristics of the outputs are shown in Table 1 1 https reference digilentinc com _detail reference programmable logic cmod s7 cmod s7 power png id reference 3Aprogrammable logic 3Acmod...

Страница 5: ...to decompress the bitstream itself during configuration Depending on design complexity compression ratios of 10x can be achieved Bitstream compression can be enabled within the Xilinx tools to occur d...

Страница 6: ...l purpose user I O pins after FPGA configuration and can be used like any other FPGA I O https reference digilentinc com _detail reference programmable logic cmod s7 cmod s7 flash png id reference 3Ap...

Страница 7: ...ence manual Figure 5 1 USB UART Bridge The Cmod S7 includes one RGB LED 4 individual LEDs and 2 push buttons as shown in Figure 6 1 The push buttons are connected to the FPGA via series resistors to p...

Страница 8: ...cting to breadboards and custom fixtures The pins have 100 mil spacing and the entire module is 0 7 inches by 3 05 inches Headers J1 and J3 are separated by 700 mil lengthwise along the Cmod measured...

Страница 9: ...r if a user accidentally drives a signal that is supposed to be used as an input The downside to this added protection is that these resistors limit the maximum switching speed of these signals to 25...

Страница 10: ...2 6 pin headers Each 12 pin Pmod connector provides two 3 3V VCC signals pins 6 and 12 two Ground signals pins 5 and 11 and eight logic signals as sown in Figure 8 1 The VCC and Ground pins can deliv...

Страница 11: ...ilentinc com technology partners Distributors https store digilentinc com our distributors Our Partners Technical Support Forum https forum digilentinc com Reference Wiki https reference digilentinc c...

Страница 12: ...ps reference digilentinc com reference programmable logic cmod s7 reference manual 12 12 https instagram com digilentinc https github com digilent https www reddit com r digilent https www linkedin co...

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