Athena IIII User Manual Rev A.00
www.diamondsystems.com
Page
55
Page 0, Base + 15
Write Counter/Timer Control Register
Bit No.
7
6
5
4
3
2
1
0
Name
CTRNO
LATCH
GTDIS
GTEN
CTDIS
CTEN
LOAD
CLR
Reset
0
0
0
0
0
0
0
0
This register is used to control the counter/timers. A counter is selected with bit 7, and then a 1 is written to any
ONE of bits 6
– 0 to select the desired operation for that counter. The other bits and associated functions are not
affected. Thus only one operation can be performed at a time.
CTRNO
Counter no., 0 or 1
LATCH
Latch the selected counter so that its value may be read. The counter must be latched before it is
read. Reading from registers 12-14 returns the most recently latched value. If you are reading
Counter 1 data, read only Base + 12 and Base + 13. Any data in Base + 14 will be from the
previous Counter 0 access.
GTDIS
Disable external gating for the selected counter.
GTEN
Enable external gating for the selected counter. If enabled, the associated gate signal GATE0 or
GATE1 controls counting on the counter. If the GATEn signal is high, counting is enabled. If the
GATEn signal is low, counting is disabled.
CTDIS
Disable counting on the selected counter. The counter will ignore input pulses.
CTEN
Enable counting on the selected counter. The counter will decrement on each input pulse.
LOAD
Load the selected counter with the data written to Base + 12 through Base + 14 or Base + 12 and
Base + 13 (depending on which counter is being loaded).
CLR
Clear the current counter (set its value to 0).
Page 0, Base + 15
Read FPGA Revision Code
Bit No.
7
6
5
4
3
2
1
0
Name
REV7
REV6
REV5
REV4
REV3
REV2
REV1
REV0
Reset
0
0
0
0
0
0
0
0
REV7-0 Revision code, read as a 2-digit hex value. The first rev of this FPGA should be 0x48.