Athena IIII User Manual Rev A.00
www.diamondsystems.com
Page
51
Base + 6
Write
DAC LSB
Bit No.
7
6
5
4
3
2
1
0
Name
DA7
DA6
DA5
DA4
DA3
DA2
DA1
DA0
Reset
0
0
0
0
0
0
0
0
DA7
–0
D/A data bits 7 - 0; This register stores the DA LSB. D/A data is an unsigned 12-bit value. This
register must be written to before the MSB, since writing the MSB updates the DAC immediately.
(Unless DASIM is enabled)
Base + 6
Read
A/D Channel and FIFO Status
Bit No.
7
6
5
4
3
2
1
0
Name
FD7/FD11 FD6/FD10 FD5/FD09 FD4/FD08 FD3/OVF
FD2/FF
FD1/HF
FD0/EF
Reset
0
0
0
0
0
0
0
0
FD7
–0
When EXFIFO = 0 (Basic Mode, See Register Description for Page 2 Base+12)
Current FIFO depth. This value indicates the number of A/D values currently stored in the FIFO.
FD11
–08 When EXFIFO = 1 (Enhanced Mode, See Register Description for Page 2 Base+12)
Current FIFO depth MSB. This value indicates the upper 4 bits of the number of A/D values
currently stored in the FIFO.
OVF
FIFO Overflow bit. This bit indicates that the FIFO has overflowed, meaning that the A/D circuit
has attempted to write data to it when it is full. This condition occurs when data is written into the
FIFO faster than it is read out.
When overflow occurs, the FIFO will not accept any more data until it is reset. The OVF condition
is sticky, meaning that it remains true until the FIFO is reset, so the application program will be
able to determine if overflow occurs. If overflow occurs, then you must either reduce the sample
rate or increase the efficiency of your interrupt routine and/or operating system.
FF
FIFO Full Bit. The next conversion will result in an overflow.
HF
FIFO Half Full Bit. FIFO is at least half full containing at least 1k words of A/D data.
EF
FIFO Empty. FIFO is empty.