Data Acquisition Circuitry I/O Map
Overview
The data acquisition circuitry on Athena II occupies 16 bytes in I/O memory space. The default address range is
280h (base address) to 28Fh.
The data acquisition FPGA can be enabled/disabled in the BIOS under the Advanced menu. Scroll down to the
“FPGA Mode” option and select “Enabled” or “Disabled,” accordingly. If the FPGA is disabled you will not be
able to interact with the data acquisition circuit. The FPGA can also be enabled or disabled programmatically
through the CPLD.
Register Map Page Summary
The following table summarizes the DAC register functions. The registers are paged to allow access to enhanced
functions. There are three register pages and the desired page is selected using the A/D gain and scan settings
register, Base+3, bits PG0-PG1, provided the board is in enhanced mode.
Page 0
Base +
Write Function
Read Function
0
Command
A/D LSB
1
Not used
A/D MSB
2
A/D channel
A/D channel
3
A/D gain/page select/scan settings
A/D gain and status
4
Interrupt/DMA/counter control
Interrupt/DMA/counter control
5
FIFO threshold
FIFO threshold
6
DAC LSB
A/D Channel and FIFO status
7
DAC MSB + channel no.
Analog operation status
8
Digital I/O port A
Digital I/O port A
9
Digital I/O port B
Digital I/O port B
10
Digital I/O port C
Digital I/O port C
11
Digital I/O control
Digital I/O control
12
Counter/timer D7-0
Counter/timer D7-0
13
Counter/timer D15-8
Counter/timer D15-8
14
Counter/timer D23-16
Counter/timer D23-16
15
Counter/timer control
FPGA revision code
Page 1
Base +
Write Function
Read Function
12
Trim DAC data/EEM data
EEM data
13
EEPROM command/Trim DAC address
EEM command address
14
Auto-CAL/Trim DAC
Trim DAC/EEM/Auto-Cal status
15
Write enable
Page 1 select read back check
Page 2
Base +
Write Function
Read Function
12
ADC expanded FIFO
ADC expanded FIFO
13
ADC control
ADC control
14
-
-
15
-
Page 2 select read back check
Diamond Systems Corporation
Athena II User Manual
Page 51
