DFI 586TXD, Руководство пользователя

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Cache Memory
The 586TXD system board can
support 512KB pipeline burst, direct
map write-back cache SRAM. Your
system board comes with a 512KB
cache, which is the maximum
cache memory supported by the
system board, mounted at locations
U5 and U6. One SRAM is mounted
on location U7 for tag SRAM to
store the cacheable addresses.
Processor Installation
The 586TXD allows for easy installation of processors. Make sure all jump-
ers are set correctly before applying power or you may damage the proces-
sor or system board. Use a needle-nosed plier to move the jumpers if nec-
essary.
Jumper JP28 is used to set the external system bus clock of your proces-
sor. Refer to the following pages for the external system bus clock that
corresponds to your processor and set this jumper accordingly. The clock
generator will determine the external bus clock that must be sent to the
processor through this setting.
Jumper JP1 and JP2 are used to set the frequency ratio of your processor.
Refer to the following pages for the frequency ratio that corresponds to your
processor and set these jumpers accordingly.
After setting these jumpers, an Intel processor will multiply the external bus
clock by the frequency ratio to become the internal clock speed. Internal
clock speed is the commonly used speed of Intel processors in the market
and is the actual operating clock of the processor (external bus clock x
frequency ratio = internal clock speed).