Designsoft TINALab II, Быстрый старт

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VGA DISPLAY PORT
The FPGA can generate a video signal for display on a VGA monitor. When the FPGA is
generating VGA signals, the FPGA outputs two bits each of red, green, and blue color information
to a simple resistor-ladder DAC. The outputs of the DAC (J11) are sent to the RGB inputs of a
VGA monitor along with the horizontal and vertical sync pulses (/HSYNC, /VSYNC) from the
FPGA. You have to create a VGA driver circuit for your TINALab FPGA board to actually display
a 64-color image.
NET "red0" LOC = "P134";
NET "red1" LOC = "P133";
NET "green0" LOC = "P132";
NET "green1" LOC = "P131";
NET "blue0" LOC = "P130";
NET "blue1" LOC = "P129";
NET "vsync" LOC = "P124";
NET "hsync" LOC = "P126";
PS/2 MOUSE/KEYBOARD PORT
The TINALab FPGA Board provides a PS/2-style interface (mini-DIN connector J10) to either a
keyboard or a mouse. The FPGA receives two signals from the PS/2 interface: a clock signal and a
serial data stream that is synchronized with the falling edge of the clock. Older keyboards or mice
work from 5V. In this case the JP5 jumper should be close pin 2, 3.
NET "PS2Clk"
LOC = "P44";
NET "PS2Data" LOC = "P46";
R/2R LADDER DAC
D/A converter converts digital quantities to an analog voltage. FPGA drives a R/2R ladder
resistive network to generate analog signal on JP3. If the code 0001 (DAC3..1=000, DAC0 = 1) is
applied to the inputs of the R/2R network, the output voltage will be approximately 0.21V. From
this step voltage, the output voltage of the ladder network can be calculated by 0.21V by number
applied, in range of 0 to 15. DAC0 the least and DAC3 the most significant value in the binary
representation.
NET "DAC0" LOC = "P54";
NET "DAC1" LOC = "P56";
NET "DAC2" LOC = "P58";
NET "DAC3" LOC = "P59";