79
TC94A92FG Block Diagram
TC94A92FG
2009-05-27
4
Block Diagram
PWM
5bit DAC
D
ig
it
al
e
qu
aliz
e
r
A
u
to
ma
ti
c a
dj
ust
men
t
ci
rcu
it
R
O
M
R
AM
Synchronous
guarantee EFM
decoder
E
rr
or
C
or
re
c
ti
on
A
d
dr
e
ss
Subcode
decoder
Audio out
Digital out
C
L
V
se
rv
o
Tracking
Error
(TE&SBAD)
Focus
Error
(FE)
RF
Auto laser
Power Cont.
(APC)
Reference
Voltage
gene.(VRO)
Auto Gain
Cont.(AGC)
DC level
DET(RFDC)
VREF
PVREF
TNi
TPi
FPi1
FPi2
FNi1
FNi2
T
Ro
D
M
o
FM
o
Fo
o
FS
M
o
Ni
T
(F
E
i/
S
B
AD
/
R
F
D
C)
1
0
bi
t AD
C
MDi
LDo
RFEQo
AGCi
RF Ripple
DET.(RFRP)
RFRPi
VRo
RFRP
R
F
RP
SBAD
RF
DC
FEI
TEI
Reference
Voltage(APC)
Bias circuit
R
F
Z
i
RESiN
RVSS3
RVDD3
PLL
TMAX
VCO
E
FM
s
lic
er
+
-
PVREF
T
MA
X
P
D
o
L
P
F
N
L
P
F
o
PVREF
VC
oF
P
V
RE
F
A1
MX
MY
MZ
MAC
A0
AY
AX
A2
register
X0/X1/X2
Y0/Y1/Y2
ALU
Bus
Switch
C-Pointer
register
Y-Pointer
register
A3
X-Pointer
register
Address Calc.
2sets
YRAM
4kw
(24bit)
X-Bus
Y-Bus
40bit
XRAM
4kw
(24bit)
ERAM
4kw
(24bit)
CROM
4kw*11=44kw
(24bit)
PRAM
1024w
(40bit)
PROM
4kw*9=36kw
(40bit)
Ge
n
er
al
I
/O
I/
F
SRAM I/F
SRAM
512kbit
(4kw*128bit)
MCU I/F
Pi
o
0-7
In
tr
up
t
C
o
nt
.
IRQ
Program
Control
Instruction
Decoder
round & limit
round & limit
TEi
VREF
+
-
+
-
4KB SRAM
Co
nt
ro
l
Se
rvo
A
V
S
S
3
A
V
D
D
3
IP
/
AT
T
V
D
D
M
1
Resume
VDD1
VSS1
RFo
IO
_CT
R
DCoFC
RF-EQ
V
C
o
i
For
DSP
TEZI
F
Mo
S
RFRP
FEI
SRAM
512kbit
(4kw*128bit)
/S
RA
M
S
T
B
Pio0
Pio7
Pio6
Pio5
Pio4
Pio3
Pio2
Pio1
T
E
S
T
/
R
S
T
DSP-VCO
SLCo
RFi
MS
/CCE
B
U
CK
/
CL
K
/
S
CL
B
U
S
3
/
Si
/
S
D
A
BUS
2
/
S
o
B
U
S
1
/
M
S
2
BUS
0 /
P
io
1
5
V
D
D
3
V
D
D
1
VS
S1
O
SC
Cl
o
ck
G
en
Fo
r CD/DAC
16
.9M
H
z
XVDD3
XVSS3
M
ul
ti
-b
it
Δ
Σ
D
A
co
nve
rter
DVSS3L
Lo
DVDD3L
DVDD3R
Ro
DVSS3R
Pi
o9
P
io
11
Pi
o8
P
io
10
C
D
M
o
N0
C
D
M
o
N1
C
D
M
o
N2
C
D
M
o
N3
VS
S1
VD
D
1
General I/O
I/F
Pio8-14
IO_CTR
CD monitor
DF
To AudioDAC
Equalizer Output Control
Stepping
Motor
Control
I2C
UART
All manuals and user guides at all-guides.com
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