62
Q311 : PLL1705
Mode Control Interface
( ) PLL1706
XT1
SR
FS2
FS1
CSEL
PLL2
PLL1
OSC
XT2
MCKO1
MCKO2
SCKO0
Divider
Divider
Divider
SCKO1
SCKO2
SCKO3
Reset
Power Supply
VCC AGND VDD1–3 DGND1–3
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
DD
1
SCKO2
SCKO3
DGND1
FS1
FS2
SR
V
CC
AGND
XT1
V
DD
3
SCKO0
SCKO1
DGND3
DGND2
MCKO2
MCKO1
V
DD
2
CSEL
XT2
(TOP VIEW)
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME
NO.
I/O
DESCRIPTION
AGND
9
–
Analog ground
CSEL
12
IN
SCKO1 frequency selection control(1)
DGND1
4
–
Digital ground 1
DGND2
16
–
Digital ground 2
DGND3
17
–
Digital ground 3
FS1(MD)
5
IN
Sampling frequency group control in PLL1705, data input for serial control in PLL1706(1)
FS2(MC)
6
IN
Sampling frequency group control in PLL1705, bit clock input for serial control in PLL1706(1)
MCKO1
14
OUT
27-MHz master clock output 1
MCKO2
15
OUT
27-MHz master clock output 2
SCKO0
19
OUT
System clock output 0 (33.8688 MHz fixed)
SCKO1
18
OUT
System clock output 1 (selectable for 44.1 kHz)
SCKO2
2
OUT
System clock output 2 (256 fS)
SCKO3
3
OUT
System clock output 3 (384 fS)
SR(ML)
7
IN
Sampling rate control in PLL1705, load strobe input for serial control in PLL1706(1)
VCC
8
–
Analog power supply, 3.3 V
VDD1
1
–
Digital power supply 1, 3.3 V
VDD2
13
–
Digital power supply 2, 3.3 V
VDD3
20
–
Digital power supply 3, 3.3 V
XT1
10
IN
27-MHz crystal oscillator, or external clock input
XT2
11
OUT
27-MHz crystal oscillator, must be OPEN for external clock input mode
(1) Schmitt-trigger input with internal pulldown.
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