15
1
LRCK
I
LRCK clock input (fs)
2
DATA
I
Data input
3
BCK
I
Bit clock input for data
4
CLKO
O
System clock, buffer output
5
XTI
I
X'tal oscillator connect or ext. clock input
6
XTO
O
X'tal oscillator connect
7
DGND
−
Digital GND
8
V
DD
−
Digital power 5V
9
Vcc2R
−
Analog power 5V
10
AGND2R
−
Analog GND
11
EXTR
O
Rch analog out amp, common
12
NC
−
NC
13
VoutR
O
Rch analog V-out
14
AGND1
−
Analog GND
15
Vcc1
−
Analog power 5V
16
VoutL
O
Lch analog V-out
17
ZEROR
O
Rch zero-data flag (open drain)
18
EXTL
O
Lch analog out amp, common
19
AGND2L
−
Analog GND
20
Vcc2L
−
Analog power 5V
21
ZEROL
O
Lch zero-data flag (open drain)
22
RST
I
Reset, L:DF and
∆
-
Σ
modulator reset
23
CS/IWO
I
Chip select/Input format select
24
MODE
I
Mode control select (H: Soft, L: Hard)
25
MUTE
I
Mute control
26
MD/DM0
I
Mode cont. data/De-emphasis select 1
27
MC/DM1
I
Mode cont. BCK/De-emphasis select 2
28
ML/IIS
I
Mode cont. latch/Input format select
Pin
No.
Name
Function
I/O
PCM1735E Terminal Function
PCM1735E
(for DCD-485 : IC301)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
LRCK
DATA
BCK
CLKO
XTI
XTO
DGND
V
DD
Vcc2R
AGND2R
EXTR
NC
VoutR
AGND1
ML/IIS
MC/DM1
MD/DM0
MUTE
MODE
CS/IWO
RST
ZEROL
Vcc2L
AGND2L
EXTL
ZEROR
VoutL
Vcc1
BU2616F (E2) (for DCD-685 : IC102)
8
9
11
10
IF IN
P3
Vss
PD2
PD1
V
DD
FM IN
AM IN
P2
P1
P0
Reference Divider
Prescaler
Shift Register Latch
I/O
CTL
Counter
If Count
CTL
12bit Main Count
Comparator
Phase
Det
XIN
XOUT
CE
CK
DA
DO
SD
P0
P1
P2
P3
IF IN
Vss
V
DD
PD2
PD1
FM IN
AM IN
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2
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