72
AVR-4308CI
APPA300 (AC : IC301)
Block Diagram
No.
Pin Name
Pin Name
No.
1
ROUT
51
R10IN
2
COUT
52
L13IN
3
LS OUT
53
L11IN
4
RS OUT
54
R13IN
5
LB OUT
55
R11IN
6
RB OUT
56
GND
7
S WOUT
57
REC_B1R
8
SUB_LOUT
58
REC_B1L
9
SUB_ROUT
59
REC_A4R
10
SUB_LIN
60
REC_A4L
11
SUB_RIN
61
REC_A3R
12
V +
62
REC_A3L
13
L1IN
63
REC_A2R
14
V -
64
REC_A2L
15
R1IN
65
REC_A1R
16
ADR
66
REC_A1L
17
L2IN
67
VDDOUT
18
DCCAP_L
68
DATA
19
R2IN
69
CLOCK
20
DCCAP_R
70
LATCH
21
L3IN
71
MUTE
22
DCCAP_C
72
ROUT_ADC
23
R3IN
73
LOUT_ADC
24
DCCAP_LS
74
GND
25
L4IN
75
LBDIN
26
DCCAP_RS
76
RBDIN
27
R4IN
77
LSCIN
28
DCCAP_LB
78
RSCIN
29
L5IN
79
LBCIN
30
DCCAP_RB
80
RBCIN
31
R5IN
81
GND
32
DCCAP_SW
82
LAIN
33
L6IN
83
RAIN
34
DCCAP
_SUBL
84
CAIN
35
R6IN
85
LSAIN
36
DCCAP
_SUBR
86
RSAIN
37
L7IN
87
LBAIN
38
GND
88
RBAIN
39
R7IN
89
SWAIN
40
GND
90
GND
41
L8IN
91
LBIN
42
GND
92
RBIN
43
R8IN
93
CBIN
44
GND
94
LSBIN
45
L9IN
95
RSBIN
46
GND
96
LBBIN
47
R9IN
97
RBBIN
48
L12IN
98
SWBIN
49
L10IN
99
GND
50
R12IN
100
LOUT
1
30
31
50
80
81
100
51
Input
S
el
ect
or
RE
C
A
RE
C
B
Lout
Rout
Cout
LSout
RSout
LBout
RBout
SWout
Multi-
SWin
Multi-
RBin
Multi-
LBin
Multi-
RSin
Multi-
LSin
Multi-
Cin
Control Logic
Data Clock Latch
M
ult
i-Ri
n
M
ult
i-L
in
Lout for
ADC
Rout for
ADC
Stereo-
Lin
Input Selector Gain :
0 / -3 / -6 / -9 / -12dB
/ Mute
Main Volume :
+31.5 to -95dB / 0.5dBstep
RE
C
A
RE
C
B
ADR
MUTE
Sub-Lout
Sub-Rout
SUb Volume :
+31 to -94dB
/ 1dBstep
S
ub-
R
in
S
ub-
Li
n
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