58
AVR-4308CI
M3062LFGPGP (DI: IC951)
M3062LFGPGP Terminal Function
Pin
Pin Name
Symbol
I/O Type
Det
Op
(Int.)
Op
(Ext.)
Res
Function
1
P94/TB4
FPGAWRITE
O
C
-
-
-
Z
AUDIO FPGA rewrite control (ACTIVE"L")
2
P93/TB3
DIRCE
O
C
-
-
-
Z
DIR control pin (LC89057W-VF4A)
3
P92/SOUT3 DIRDIN
O
C
-
-
-
Z
DIR control pin (LC89057W-VF4A)
4
P91/SIN3
DIRDOUT
I
-
Lv
-
Eu
Z
DIR control pin (LC89057W-VF4A)
O
C
-
-
-
Z
DIR control pin (LC89057W-VF4A)
-
-
-
-
-
-
GND (Ext. data bus bit width switching, 16bit : L)
-
-
-
-
Ed
-
"Single-chip / Micro-processor mode switching (Normal single-chip : L,
Rewrite boot program start : H input set)"
O
C
-
-
Ed
Z
Video encoder reset (ADV7320)
O
C
-
-
Ed
Z
Video encoder reset (ADV7430)
I
-
Lv
-
Eu
L
Reset input
O
-
-
-
-
-
Oscillator connection
-
-
-
-
-
-
GND
I
-
-
-
-
-
Oscillator connection
-
-
-
-
-
-
+3.3V
I
-
-
-
-
-
Not used (Fixed to H)
16
P84/INT2
CEC̲IN
I
-
E ↓ &L
-
Eu
Z
CEC-D signal input pin (SII9185)
17
P83/INT1
ACKSIMO
I
-
E ↓ &L
-
Ed
Z
MAIN-SUB μcom comm. Control input pin
18
P82/INT0
SUB BDOWN
I
-
E ↓ &L
Eu
Z
Power down detect (Power down : L)
19
P81
IP RST/
O
C
-
-
Ed
Z
IP CONV (FLI2310) reset
20
P80
GUI WRITE
O
-
-
-
-
Z
GUI ROM rewrite control (ACTIVE"L")
21
P77
(GUI RST̲SUB)/SUBTDO
I
-
-
-
-
Z
(For GUI RST from SUB, Not used)/PLD rewrite control(JTAG)
22
P76
MPLD CS MAIN/SUBTMS
O
C
-
-
Eu
Z
MAIN FPGA (PLD) control pin/PLD rewrite control (JTAG)
23
P75
MPLD DATA/SUBTDI
O
C
-
-
Eu
Z
MAIN FPGA (PLD) control pin/PLD rewrite control (JTAG)
24
P74
MPLD CLK/SUBTCK
O
C
-
-
Eu
Z
MAIN FPGA (PLD) control pin/PLD rewrite control (JTAG)
25
P73/CTS2
VIDEO POWER
O
C
-
-
Ed
Z
VIDEO POWER control output (H : ON)
26
P72/CLK2
DIGITAL POWER
O
C
-
-
Ed
Z
DIGITAL POWER control output (H : ON)
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