Turbo PMAC2 Hardware Reference Manual
Option 1: Additional MACRO Interface ICs
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Option 1A provides the first additional MACRO interface IC (2 total) for 16 additional
MACRO nodes, 8 additional servo nodes and 8 additional I/O nodes (32 nodes total, 16 servo
and 16 I/O). The key component on the board is U54.
Option 1B provides the second additional MACRO interface IC (3 total) for 16 additional
MACRO nodes, 8 additional servo nodes and 8 additional I/O nodes (48 nodes total, 24 servo
and 24 I/O). The key component on the board is U55. Option 1A is a pre-requisite.
Option 1C provides the third additional MACRO interface IC (4 total) for 16 additional
MACRO nodes, 8 additional servo nodes and 8 additional I/O nodes (64 nodes total, 32 servo
and 32 I/O). The key component on the board is U56. Options 1A and 1B are pre-requisites.
Option 2: Dual Ported RAM
Dual-ported RAM provides a very high-speed communications path for bus communications with
the host computer through a bank of shared memory. DPRAM is advised if more than about 100
data items per second are to be passed between the controller and the host computer in either
direction.
Option 2 provides an 8k x 16 bank of dual-ported RAM. The key component on the board is
U28. It is not compatible with Option 2B.
Option 2B provides a 32k x 16 bank of dual-ported RAM. The key component on the board is
U28A. It is not compatible with Option 2.
Option 5: CPU & Memory Configurations
The various versions of Option 5 provide different CPU speeds and main memory sizes. Only
one Option 5xx may be selected for the board.
The CPU is a DSP5630x IC as component U1. It is currently available only as an 80 MHz device
(with computational power equivalent to a 120 MHz non-Turbo PMAC), but higher speed
versions will be available shortly.
The compiled/assembled-program memory SRAM ICs are located in U14, U15, and U16. These
ICs form the active memory for the firmware, compiled PLCs, and user-written phase/servo
algorithms. These can be 128k x 8 ICs (for a 128k x 24 bank), fitting in the smaller footprint, or
they can be the larger 512k x 8 ICs (for a 512k x 24 bank), fitting in the full footprint.
The user-data memory SRAM ICs are located in U11, U12, and U13. These ICs form the active
memory for user motion programs, uncompiled PLC programs, and user tables and buffers. These
can be 128k x 8 ICs (for a 128k x 24 bank), fitting in the smaller footprint, or they can be the
larger 512k x 8 ICs (for a 512k x 24 bank), fitting in the full footprint.
The flash memory IC is located in U10. This IC forms the non-volatile memory for the board’s
firmware, the user setup variables, and for user programs, tables, and buffers. It can be 1M x 8,
2M x 8, or 4M x 8 in capacity.
Option 5C0 is the standard CPU and memory configuration. It is provided automatically if
no Option 5xx is specified. It provides an 80 MHz CPU (120 MHz PMAC equivalent), 128k
x24 of compiled/assembled program memory, 128k x 24 of user data memory; and a 1M x 8
flash memory.
Option 5C1 provides an 80 MHz CPU (120 MHz PMAC equivalent), 128k x 24 of
compiled/assembled program memory, an expanded 512k x 24 of user data memory, and a
2M x 8 flash memory.
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Introduction
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