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PMAC-PC Hardware Reference

52

PMAC-PCI Base Board Connector Pinouts

J8 JMACH1
(60-Pin Header)
(Continued)

Front View

Pin #

Symbol

Function

Description

Notes

40

-LIM4

Input

Positive End Limit 4

8,9

41

HMFL3

Input

Home-Flag 3

10

42

HMFL4

Input

Home-Flag 4

10

43

DAC1

Output

Analog Out Pos. 1

4

44

DAC2

Output

Analog Out Pos. 2

4

45

DAC1/

Output

Analog Out Neg. 1

4,5

46

DAC2/

Output

Analog Out Neg. 2

4,5

47

AENA1/DIR1

Output

Amp-Enable/Dir. 1

6

48

AENA2/DIR2

Output

Amp-Enable/Dir. 2

6

49

FAULT1

Input

Amp.-Fault 1

7

50

FAULT2

Input

Amp.-Fault 2

7

51

+LIM1

Input

Negative End Limit 1

8,9

52

+LIM2

Input

Negative End Limit 2

8,9

53

-LIM1

Input

Positive End Limit 1

8,9

54

-LIM2

Input

Positive End Limit 2

8,9

55

HMFL1

Input

Home-Flag 1

10

56

HMFL2

Input

Home-Flag 2

10

57

FEFCO/

Output

FE/Watchdog Out

Indicator/Driver

58

AGND

Input

Analog Common

59

A+15V/OPT+V

Input

15V Supply

60

A-15V

Input

Analog –15V Supply

The J8 connector is used to connect PMAC to the first 4 channels (Channels 1, 2, 3, and 4) of servo amps,
flags, and encoders.

Note 1

: In standalone applications, these lines can be used as +5V power supply inputs to power PMAC's

digital circuitry. However, if a terminal block is available on your version of PMAC, it is preferable to
bring the +5V power in through the terminal block.

Note 2

: Referenced to digital common (GND). Maximum of + 12V permitted between this signal and its

complement.

Note 3

: Leave this input floating if not used (i.e. digital single-ended encoders). In this case, jumper (E18 -

21, E24 - 27) for channel should hold input at 2.5V.

Note 4

: + 10V, 10mA max, referenced to analog common (AGND).

Note 5

: Leave floating if not used; do not tie to AGND. In this case, AGND is the return line.

Note 6

: Functional polarity controlled by jumper(s) E17. Choice between AENA and DIR use controlled

by Ix02 and Ix25.

Note 7

: Functional polarity controlled by variable Ix25. Must be conducting to 0V (usually AGND) to

produce a '0' in PMAC software. Automatic fault function can be disabled with Ix25.

Note 8:

Pins marked -LIMn should be connected to switches at the positive end of travel. Pins marked

+LIMn should be connected to switches at the negative end of travel.

Note 9

: Must be conducting to 0V (usually AGND) for PMAC to consider itself not into this limit.

Automatic limit function can be disabled with Ix25.

Note 10

: Functional polarity for homing or other trigger use of HMFLn controlled by Encoder/Flag

Variable 2 (I902, I907, etc.) HMFLn selected for trigger by Encoder/Flag Variable 3 (I903, I908, etc.).
Must be conducting to 0V (usually AGND) to produce a 0 in PMAC software.

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Содержание PMAC PCI

Страница 1: ...PMAC PCI 3 PCI Bus Expansion w Piggyback CPU 4 4A0 603588 100 5 June 18 2010 Single Source Machine Control Power Flexibility Ease of Use 21314 Lassen Street Chatsworth CA 91311 Tel 818 998 2095 Fax 8...

Страница 2: ...amplifiers contain static sensitive components that can be damaged by incorrect handling When installing or handling Delta Tau Data Systems Inc products avoid contact with highly insulated materials...

Страница 3: ...ON HISTORY REV DESCRIPTION DATE CHG APPVD 1 UPDATED JUMPER INFO SOFTWARE SETUP 10 19 06 CP M COGUR 2 UPDATED JUMPER SETTINGS FOR E121 E122 04 27 10 CP S SATTARI 3 Opt 12 E17A E17D description 07 21 15...

Страница 4: ......

Страница 5: ...Connectors JMACH2 JMACH1 Ports 3 J9 Compare Equal Outputs Port JEQU Port 3 J30 Optional Analog to Digital Inputs JANA Port 3 J31 Optional Universal Serial Bus Port JUSB Port 3 JS1 JS2 Expansion Ports...

Страница 6: ...Enable 22 E90 Host Supplied Switch Pull Up Enable 23 E98 DAC ADC Clock Frequency Control 23 E100 Output Flag Supply Select 23 E101 E102 Motors 1 4 Amplifier Enable Output Configure 24 E109 Reserved fo...

Страница 7: ...Option 42 CPU Board Connectors 42 J2 JEXP Expansion 42 J4 JDPRAM Dual Ported RAM 42 BASE BOARD CONNECTOR PINOUTS 43 J1 Display Port Connector 43 J1 JDISP 14 Pin Connector 43 J2 Control Panel Port Conn...

Страница 8: ...C PCI Hardware Reference iv Table of Contents PMAC I Variables 56 Operation of the Non Turbo CPU 56 Configuring PMAC with Option 5C for 80 MHz Operation 59 Option 16 Supplemental Memory 60 SCHEMATICS...

Страница 9: ...PMAC PCI Hardware Reference Table of Contents v...

Страница 10: ......

Страница 11: ...3 channel differential single ended encoder input Four input flags two output flags Interface to external 16 bit serial ADC Display control panel muxed I O direct I O interface ports Buffered expansi...

Страница 12: ...n 12 Analog to Digital Converters Option 12 permits the installation of 8 or 16 channels of on board multiplexed analog to digital converters One or two of these converters are read every phase interr...

Страница 13: ...y be needed for a particular setup J5 General Purpose Digital Inputs and Outputs JOPTO Port PMAC s JOPTO connector provides eight general purpose digital inputs and eight general purpose digital outpu...

Страница 14: ...D is lit this indicates that power is applied to the 5V input when the red LED is lit this indicates that the watchdog timer has tripped and shut down the PMAC The yellow LED located beside the red an...

Страница 15: ...E74 B9 E17E C5 E75 B9 E17F C5 E85 C5 E17G C4 E87 C5 E17H C4 E88 B2 E22 A9 E89 B5 E23 A9 E90 B5 E28 C6 E98 A4 E29 A4 E100 A3 E30 A4 E101 A3 E31 A4 E102 A3 E32 A4 E109 B6 E33 A4 E110 A7 E34 A4 E111 A7 E...

Страница 16: ...PMAC PCI Hardware Reference 6 Introduction 1 2 B A 3 4 6 8 7 9 C 5 E57 E61 E65 E56 E60 E64 E55 E59 E63 E54 E58 E62 E17D E17C E17B E38 E17A E37 E29 E36 E30 E35 E31 E34 E32 E34A E33 E3 E4 E5 E6...

Страница 17: ...PMAC PCI Hardware Reference Introduction 7 PMAC Connectors...

Страница 18: ...parate isolated supplies are used E89 E90 Input Flag Supply Control If E90 connects pins 1 and 2 and E89 is ON the input flags LIMn LIMn and HMFLn are supplied from the analog A 15V supply which can b...

Страница 19: ...lt setting of 1 2 which creates a 2 45 MHz DCLK signal unless you are connecting an Acc 28 A D converter board In this case move the jumper to connect pins 2 and 3 which creates a 1 22 MHz DCLK signal...

Страница 20: ...iver IC UDN2981A or equivalent these jumpers must be changed to connect pins 2 and 3 to supply the new IC correctly E7 Machine Input Source Sink Control With this jumper connecting pins 1 and 2 defaul...

Страница 21: ...the QuadLoss signal for Encoder 6 into register XIN6 at Y E801 bit 6 Jump 2 3 to bring the QuadLoss signal for Encoder 7 into register XIN6 at Y E801 bit 6 E122 XIN7 Feature Selection Jump 1 2 to bri...

Страница 22: ...in normal operational mode Flash Memory Bank Select Jumpers The flash memory IC in location U10 on the Flex CPU board has the capacity for eight separate banks of firmware only one of which can be use...

Страница 23: ...ported RAM through JEXP expansion port Jumper connects pins 1 and 2 Note Jumper E2 is present on 108 and newer boards only Older versions could access DPRAM from either source without a jumper config...

Страница 24: ...r IC or damage to the IC will result Jump pin 1 to 2 to apply V 5V to 24V to pin 10 of U13 should be ULN2803A for sink output configuration JOPTO machine outputs M01 M08 Jump pin 2 to 3 to apply GND t...

Страница 25: ...a servo interrupt cycle scaled so that 8 388 608 equals one millisecond Since I10 has a maximum value of 8 388 607 the servo interrupt cycle time should always be less than a millisecond unless you wa...

Страница 26: ...ENA4 No jumper installed Note Low true enable is the fail safe option because of the sinking open collector ULN2803A output driver IC E17E H Amplifier Enable Direction Polarity Control E Point and Phy...

Страница 27: ...llowing error Ix12 for the selected coordinate system to control FEFCO on J8 57 Jump pin 2 to 3 to cause Watchdog timer output to control FEFCO Low TRUE output in either case 2 3 Jumper installed E29...

Страница 28: ...d CHC4 E40 E43 Software Address Control Jumpers E40 E43 control the software address of the card for serial addressing and for sharing the servo and phase clock over the serial connector Card 0 sends...

Страница 29: ...re only used to set the baud rate at power on reset Currently Flex CPU s communication baud rate is determined at power up reset by variable I54 Non standard baud rates E48 CPU Clock Frequency Control...

Страница 30: ...r Up E Point and Physical Layout Location Description Default E51 B6 Jump pin 1 to 2 to re initialize ON power up reset Remove jumper for Normal power up reset No jumper installed E54 E65 Host Interru...

Страница 31: ...B6 Jump pin 1 to 2 to allow AXIS EXPANSION INT 1 to interrupt host PC at PMAC interrupt level IR5 No jumper installed E64 B6 Jump pin 1 to 2 to allow EQU5 to interrupt host PC at PMAC interrupt level...

Страница 32: ...e changed Also see E90 No jumper E87 E88 Host Supplied Analog Power Source Enable E Point and Physical Layout Location Description Default E87 C5 Jump pin 1 to pin 2 to allow AGND to come from PC bus...

Страница 33: ...MAC Opto isolation diagram 1 2 Jumper installed E98 DAC ADC Clock Frequency Control E Point and Physical Layout Location Description Default E98 A4 Jump 1 2 to provide a 2 45 MHz DCLK signal to DACs a...

Страница 34: ...ion 1 2 Jumper installed E102 A3 CAUTION The jumper setting must match the type of driver IC or damage to the IC will result Jump pin 1 to 2 to apply GND to pin 10 of U37 AENAn EQUn should be ULN2803A...

Страница 35: ...Location Description Default E114 A3 CAUTION The jumper setting must match the type of driver IC or damage to the IC will result Jump pin 1 to 2 to apply A 15V A V as set by E100 to pin 10 of U53 AENA...

Страница 36: ...o bring the QuadLoss signal for Encoder 7 into register XIN6 at Y E801 bit 6 Jump 2 3 to bring the QuadLoss signal for Encoder 6 into register XIN6 at Y E801 bit 6 1 2 Jumper installed E122 F1 Jump 1...

Страница 37: ...fs Power Supplies Digital Power Supply 2A 5V 5 10 W Eight channel configuration with a typical load of encoders The host computer provides the 5 Volts power supply in the case PMAC is installed in its...

Страница 38: ...ns LIMn and LIMn are direction sensitive overtravel limits that must be actively held low sourcing current from the pins to ground to permit motion in their direction The direction sense of LIMn and L...

Страница 39: ...Encoder 7 RP104 6 pin Encoder 4 RP69 6 pin Encoder 8 RP106 6 pin Resistor Pack Configuration Differential or Single Ended Encoder Selection The differential input signal pairs to the PMAC PCI have us...

Страница 40: ...f using a single ended signal leave the complementary signal pins floating do not ground them However if single ended encoders are used please check the settings of the jumpers E18 to E21 and E24 to E...

Страница 41: ...e analog outputs are intended to drive high impedance inputs with no significant current draw The 220 output resistors will keep the current draw lower than 50 mA in all cases and prevent damage to th...

Страница 42: ...osite row The 34 pin connector was designed for easy interface to OPTO 22 or equivalent optically isolated I O modules Delta Tau s Acc 21F is a six foot cable for this purpose Characteristics of the J...

Страница 43: ...to 1 If this is the case they may be used as general purpose inputs by assigning M variable to their corresponding memory map locations bits of Y address FFC0 Command Inputs JOG JOG PREJ return to pre...

Страница 44: ...oder conversion table can then take the difference in the counter each servo cycle and scale it providing a value proportional to frequency and therefore to the input voltage Usually this is used for...

Страница 45: ...12 provides eight 12 bit analog inputs ANAI00 ANAI07 Option 12A provides eight additional 12 bit analog inputs ANA08 ANAI15 for a total of 16 inputs In firmware versions 1 17C and below only Option 12...

Страница 46: ...ers contain the A D results Each X and Y word is split into two 12 bit halves where the lower 12 bits work with the first A D converter set Option 12 and the higher 12 bits work with the second A D co...

Страница 47: ..._W1 and CONFIG_W2 M992 X 070A 0 24 U 3rd CONFIG_W1 and CONFIG_W2 M993 X 070B 0 24 U 4th CONFIG_W1 and CONFIG_W2 M994 X 070C 0 24 U 5th CONFIG_W1 and CONFIG_W2 M995 X 070D 0 24 U 6th CONFIG_W1 and CONF...

Страница 48: ...JANA pin 4 M1004 Y 070C 0 12 U ANAI04 image register from JANA pin 5 M1005 Y 070D 0 12 U ANAI05 image register from JANA pin 6 M1006 Y 070E 0 12 U ANAI06 image register from JANA pin 7 M1007 Y 070F 0...

Страница 49: ...Tau provides the Acc 3D cable that connects the PMAC PCI to a DB 25 connector Standard DB 9 to DB 25 or DB 25 to DB 9 adapters may be needed for a particular setup Jumper E110 selects between RS 232 a...

Страница 50: ...PMAC PCI Hardware Reference 40 Mating Connectors Machine Connections Example...

Страница 51: ...641 2 171 26 T B Ansley standard flat cable stranded 26 wire 3 Phoenix varioface module type FLKM 26 male pins P N 22 81 05 0 J5 JOPT OPTO I O 1 Two 34 pin female flat cable connector Delta Tau P N 01...

Страница 52: ...00F10 0K0 T B Ansley P N 609 1041 2 171 10 T B Ansley standard flat cable stranded 10 wire 3 Phoenix varioface module type FLKM 10 male pins P N 22 81 01 8 JANA Analog Inputs Option 1 Two 20 pin femal...

Страница 53: ...Read or Write TTL signal out 7 DB1 Output Display Data 1 8 DB0 Output Display Data 0 9 DB3 Output Display Data 3 10 DB2 Output Display Data 2 11 DB5 Output Display Data 5 12 DB4 Output Display Data 4...

Страница 54: ...Low is RESET Equiv to 16 HWCA Input Handwheel Enc A Channel 5V TTL sq pulse must use E23 CHA2 17 IPLD Output In Position Ind C S Low lights LED 18 BRLD Output Buffer Request Ind Low lights LED 19 ERL...

Страница 55: ...elect output 15 DAT6 Input Data 6 Input Data input from multiplexed accessory 16 SEL6 Output Select 6 Output Multiplexer select output 17 DAT7 Input Data 7 Input Data input from multiplexed accessory...

Страница 56: ...al Clock Diff I O high TRUE 21 SERVO Bidirectional Servo Clock Diff I O low TRUE 22 SERVO Bidirectional Servo Clock Diff I O high TRUE 23 PHASE Bidirectional Phase Clock Diff I O low TRUE 24 PHASE Bid...

Страница 57: ...TRUE sourcing 18 GND Common PMAC common 19 MO7 Output Machine output 7 20 GND Common PMAC common 21 MO6 Output Machine output 6 22 GND Common PMAC common 23 MO5 Output Machine output 5 24 GND Common P...

Страница 58: ...Pos Axis 1 for resolver 4 CHA3 Input Enc A Chan Pos Axis 3 for resolver 5 CHB3 Input Enc B Chan Pos Axis 3 for resolver 6 CHC3 Input Enc C Chan Pos Axis 3 for resolver 7 E63 Input Interrupt IR4 Interr...

Страница 59: ...n Neg 2 3 16 CHA8 Input Encoder A Chan Neg 2 3 17 CHC5 Input Encoder C Chan Pos 2 18 CHC6 Input Encoder C Chan Pos 2 19 CHC5 Input Encoder C Chan Neg 2 3 20 CHC6 Input Encoder C Chan Neg 2 3 21 CHB5 I...

Страница 60: ...k is available on your version of PMAC it is preferable to bring the 5V power in through the terminal block Note 2 Referenced to digital common GND Maximum of 12V permitted between this signal and its...

Страница 61: ...an Neg 2 3 16 CHA4 Input Encoder A Chan Neg 2 3 17 CHC1 Input Encoder C Chan Pos 2 18 CHC2 Input Encoder C Chan Pos 2 19 CHC1 Input Encoder C Chan Neg 2 3 20 CHC2 Input Encoder C Chan Neg 2 3 21 CHB1...

Страница 62: ...s available on your version of PMAC it is preferable to bring the 5V power in through the terminal block Note 2 Referenced to digital common GND Maximum of 12V permitted between this signal and its co...

Страница 63: ...Optional Pin Symbol Function Description Notes 1 ANAI00 Input Analog Input 0 0 5V or 2 5V range 2 ANAI01 Input Analog Input 1 0 5V or 2 5V range 3 ANAI02 Input Analog Input 2 0 5V or 2 5V range 4 ANAI...

Страница 64: ...1 Select for Chan 1 2 3 4 5 CNVRT01 Output A to D Convert ADC convert sig Chan 1 2 3 4 6 ADCIN1 Input A to D Data ADC data for Chan 1 2 3 4 7 OUT1 Output Chan Select Bit Amp Enable Dir for Chan 1 8 OU...

Страница 65: ...r Chan 5 12 HF46 Input Amp Fault Amp Enable Dir for Chan 6 13 HF47 Input Amp Fault Amp Enable Dir for Chan 7 14 HF48 Input Amp Fault Amp Enable Dir for Chan 8 15 5V Output 5V Supply Power supply out 1...

Страница 66: ...few issues to note The Flex CPU requires the use of V1 17 or newer firmware There are few differences between the previous V1 16H firmware and the V1 17 firmware other than the addition of internal s...

Страница 67: ...o the PMAC The PMAC will respond with five data items the last of which is CLK Xn where n is the multiplication factor from the 20 MHz crystal frequency not 10 MHz n should be equivalent to I46 1 2 if...

Страница 68: ...Baud Rate for 20MHz Baud Rate for 40MHz Baud Rate for 60MHz ON ON ON ON Disabled Disabled Disabled OFF ON ON ON 300 600 900 ON OFF ON ON 400 800 1200 OFF OFF ON ON 600 1200 1800 ON ON OFF ON 800 1600...

Страница 69: ...ards This has always been the case for PMAC2 boards but with other CPU boards the card number on PMAC 1 boards has been determined by the settings of jumpers E40 E43 Jumpers E40 E43 on a PMAC 1 board...

Страница 70: ...aud divider algorithm is valid only if the PMAC has been jumpered for 40 MHz operation E48 OFF M98 X FFF2 0 12 M99 X FFFD 0 4 OPEN PLC 1 CLEAR M99 3 Set x4 frequency multiplication 80 MHz M98 2 M98 1...

Страница 71: ...acked static RAM It maps into the PMAC and PMAC2 at addresses A000 to BFFF on both the X and Y data buses an 8k x 48 block of address space Addresses Y BC00 to Y BFFF are double mapped with the main f...

Страница 72: ...PMAC PCI Hardware Reference 62 Schematics SCHEMATICS...

Страница 73: ...PMAC PCI Hardware Reference Schematics 63...

Страница 74: ...PMAC PCI Hardware Reference 64 Schematics...

Страница 75: ...PMAC PCI Hardware Reference Schematics 65...

Страница 76: ...PMAC PCI Hardware Reference 66 Schematics...

Страница 77: ...PMAC PCI Hardware Reference Schematics 67...

Страница 78: ...PMAC PCI Hardware Reference 68 Schematics...

Страница 79: ...PMAC PCI Hardware Reference Schematics 69...

Страница 80: ...PMAC PCI Hardware Reference 70 Schematics...

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