Dell PowerEdge M710 Technical Guide
47
Type
NAND Flash
Purpose
This device stores the iDRAC6 kernel and other
data for system management.
Can user programs or operating system write
data to it during normal operation?
Yes. Under software control.
How is data input to this memory?
I2C bus from iDRAC
How is this memory write protected?
Only the iDRAC can write to the chip
HDD Backplane Firmware (SEP) Memory
Details
Size
32KB
Type
Flash
Purpose
Interface between the RAID controller and the
hard drives as well as a controller for the HDD
status LED
Can user programs or operating system write
data to it during normal operation?
No; a special (not available to customers) DOS
utility is needed to flash the application code,
and the boot block is cable flashed only
How is data input to this memory?
Cable flash to flash entire chip or a special utility
(not available to customers) to flash in DOS
How is this memory write protected?
Software write protected; no hardware protection
pin
iDRAC6 Enterprise SPI Flash
Details
Size
2MB
Type
SPI Flash
Purpose
There is boot code that is used by the iDRAC6
Enterprise management controller. Also contains
the Life Cycle Log which contains server
management data unique to the run-time events
of the server itself.
Can user programs or operating system write
data to it during normal operation?
No
How is data input to this memory?
Flashed in the factory or using Dell flash utility.
Also written to by the iDRAC6 Enterprise
controller to make Life Cycle Log (LCL) entries.
How is this memory write protected?
Software write protected
TPM (for boards shipped outside of China)
Details
Size
Unspecified size of user ROM, RAM, EEPROM;
128 bytes of OTP memory included
Type
ROM, RAM, EEPROM
Purpose
Trusted Platform Module NV storage. May be used
to securely store user data.
Can user programs or operating system write
data to it during normal operation?
Yes, OSes and applications that conform to the
TCG standard can write data to the TPM during
normal operation. Access to the NV Storage is
controlled by the TPM owner.
How is data input to this memory?
TCG TPM Specification defined command
interface.
How is this memory write protected?
As defined by the TCG TPM Specification,