DEC DECstation 316+, Руководство по обслуживанию

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Troubleshooting 2–9
When several bursts of beeps are generated, listen carefully and
remember the numeric beep code pattern. This pattern establishes
the secondary level of beep codes. Table 2–3 lists the secondary
beep codes and the test in-progress or test failure that corresponds
to the numeric beep code pattern. For example, "2-1-4" (a burst of
two beeps, a single beep, and a burst of four beeps) indicates that
a failure of bit 3 in the first 64K of RAM has been detected.
Table 2–3 Secondary Beep Codes
Beep Code Description of Test or Failure
1-1-3 CMOS write/read test in-progress or failure
1-1-4 BIOS ROM checksum test in-progress or failure
1-2-1 Programmable Interval Timer test in-progress or
failure
1-2-2 DMA initialization test in-progress or failure
1-2-3 DMA page register write/read test failure
1-3-1 RAM refresh verification test in-progress or failure
1-3-3 1st 64K RAM chip of data line failure - multi-bit
1
1-3-4 1st 64K RAM odd/even logic failure
1-4-1 1st 64K RAM address line failure
1-4-2 1st 64K parity test in-progress or failure
2-1-1 1st 64K RAM chip or data line failure - bit 0
2-1-2 1st 64K RAM chip or data line failure - bit 1
2-1-3 1st 64K RAM chip or data line failure - bit 2
2-1-4 1st 64K RAM chip or data line failure - bit 4
2-2-1 1st 64K RAM chip or data line failure - bit 4
2-2-2 1st 64K RAM chip or data line failure - bit 5
1
Any of the RAM failures can be caused by a SIMM not being properly seated in
its socket.