DM9000A
APPLICATION NOTES
Preliminary 19
Version: DM9000A-AN-V121
November 27, 2007
4 Reset Operation and PHY Power-down Mode
The DM9000A can be reset by either hardware reset or software reset. A hardware reset can
be accomplished by the power-on reset PWRST# pin 40. A software reset can be
accomplished by setting the network control register (NCR REG. 00) RST Bit [0] = 1.
The internal PHY of the DM9000A can be powered down by writing "1" to PHYPD (the Bit [0]
of the GPR register), or by setting the Power-down Bit [11] = 1 in the PHY basic mode control
register (BMCR PHY REG. 00). In the power-down state, the power consumption is reduced
to a minimum under 21mA/ 3.3V.
4.1 Power On Reset
An active low signal is used to reset the DM9000A LAN chip. The PWRST# pin 40 is asserted
low for at least 20 ms. All of the MAC and PHY registers will be reset to the default values and
the hardware strap pins will also be latched. The DM9000A is ready after 5 us when this pin is
de-asserted and then the data will be downloaded from the EEPROM.
4.2 Software Reset
A software reset can be accomplished by setting RST Bit [0] = 1 in the network control register,
NCR REG. 00. After the reset, some registers will be reset to their default value. And the
DM9000A needs only 10 us for a software reset.
4.3 PHY Power Down Mode
In the power-down (power-saving) mode, the DM9000A will disable all the TX&RX functions.
And, it’s almost the same as the PHY SLEEP mode powered down all circuit, except oscillator
and clock generator circuit. But, it’s different to the Power Reduced mode which the TX circuit
still sends out fast link pulse with min. power consumption and wakes up if a valid signal is
detected, automatically.
