dspblok™ 21469 User Manual
Page 8
Memory
The ADSP-21469 includes an on board DDR2 DRAM controller. Unlike earlier SHARC processors, the
DRAM interface is largely independent of the external data bus. On the dspblok 21469, the only overlap is
MS0#, which is not available because its address is assigned to DDR2_CS#.
The dspblok 21469 uses a 1Gb (64M x 16) DDR2 DRAM. DDR2 memory is much faster and typically much
larger than older SDRAM. PC board layout is non trivial. The dedicated DDR2 interface of the ADSP-21469
has been carefully laid out with respect to trace length, signal integrity, and bus isolation so that the DDR2
operates reliably at maximum speed. The CD includes examples of DDR2 register configuration code.
A 16Mbit serial flash memory may be used to bootload the DSP. There is a pre-installed bootloader program
that resides in the flash. This program accepts standard ADI loader files (SPI, slave, binary, 8 bit) and can be
uploaded with a Danville dspblok development board, a dspstak 21469 or any board that includes a USB
connector to JH8. If you want to manage the flash memory yourself, you can overwrite the internal
bootloader via the JTAG port. In this case, the Danville dspFlash
Blackfin & SHARC Programmer is available
for fast production programming.
64kbits of EEProm memory is also available as byte addressable user memory. For example, you might store
serial numbers, build versions or calibration values in this space.
There are other Flash/EEProm combinations available via special order. Contact Danville if you have special
memory requirement needs.
DAI & DPI
The ADSP-21469 has 20 DAI lines and 14 DPI lines. Collectively these can be thought of as two sets of
crossbar switches that connect to a wealth of peripherals. The dspblok 21469 maintains the flexibility of the
DAI and DPI by bringing out all 20 DAI and 12 of 14 DPI lines to external connections.
The DAI is completely unencumbered and can be assigned to I/O in an arbitrary manner. The DPI is slightly
restricted in that the primary SPI interface is assigned to DPI1 (MOSI), DPI2 (MISO), DPI3 (SCK), DPI5 (Flash
SS) and DPI6 (EE SS). With the exception of DPI6, these connections are necessary to support SPI master
booting. The dspblok 21469 may also be booted from an external host using SPI slave mode. In this case
DPI4 is also used as the SPIDS# line.
Data Bus
The dspblok 21469 brings out the complete asynchronous data bus including all address lines with the
exception of MS0# which would be in conflict with the DDR2 chip select.
The upper portion of MS1# is used for on-board peripherals. The lower ¾ of the address space is available.
MS2# and MS3# can also be used as FLAG2 and FLAG3, respectively. They are configured together so
MS1# might be used for the external data bus and FLAG2 & FLAG3 for other purposes.
