IM10-OS3AH
Schematics and Illustrations - 29-71.4 MHz FM Synthesizer
21
A
A
B
B
C
C
D
D
E
E
F
F
G
G
H
H
I
I
J
J
K
K
L
L
M
M
N
N
O
O
P
P
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
1
1
0
0
JU2
9.6 MHz
REFERENCE
10 MHz
REFERENCE
NOT INSTALLED
INSTALLED
JU1
OSx-3H
29-470 MHz
OSx-3A
118-159.6 MHz
NOT INSTALLED
INSTALLED
J3 C7
J4 H5
JU1 F2
JU2 L2
L1 D2
P1 C2
P2 C7
Q1 F3
Q2 F6
Q3 M2
Q4 M7
Q5 M8
Q6 M8
Q7 M9
Q8 N5
Q9 N4
Q10 N4
Q11 N3
R1 D6
DES LC
COMPONENT LOCATION TABLE
C1 D2
C2 E2
C3 E2
C4 G2
C5 H2
C6 I3
C7 I3
C8 K5
C9 K5
C10 M7
C11 M7
C12 N7
C13 N8
C14 N9
C15 F3
D1 M7
D2 M8
D3 M8
D4 M9
J1 C6
J2 C6
DES LC DES LC
R2 E3
R3 F2
R4 G6
R5 G4
R6 G5
R7 H4
R8 H3
R9 I4
R10 I2
R11 J3
R12 L6
R13 L2
R14 K3
R15 L3
R16 L3
R17 L3
R18 L6
R19 L6
R20 L6
R21 M2
R22 M3
R23 M7
R24 M8
DES LC
R25 M8
R26 M9
R27 M5
R28 M3
R29 M4
R30 N7
R31 N8
R32 N8
R33 N9
R34 N5
R35 N4
R36 N4
R37 N3
R38 I5
R39 L2
R40 N9
R41 E3
R42 I5
TP1 H2
TP2 J2
TP3 N7
TP4 N7
DES LC
TP5 N8
TP6 N9
TP7 M9
U1 F2
U2 H2
U3 H3
U4 J2
U5 N7
U6 N7
U7 N8
U8 N9
U9 N9
X1 I3
HIGHEST REFERENCE DESIGNATORS
UNUSED REFERENCE DESIGNATORS
TITLE:
DATE:
DWG No.:
BOARD No.:
DWN BY:
APRVD:
DWG REV DATE:
REVISED BY:
REV:
DANIELS
ELECTRONICS LTD
TM
VICTORIA BC.
21 APR 03
01-S-01-01-1
ENABLE
ACTIVE HIGH
JU2
U9
-----
R41
J4
X1
Q11
C15
SHANE AEBISCHER
04
50021-04
STAN P
23 APRIL 1992
OS(R/T)-3(A/H) DIGITAL BOARD SCHEMATIC DIAGRAM
-----
-----
-----
-----
-----
-----
-----
-----
-----
-----
FM/AM
SEL
FREQ
REF
DATA OUTPUT
+12V PRG
PRIORITY COR
LOCK DETECT INPUT
POWER CONTROL
CLK
CHAN SEL1 (I/P)
TCXO MOD INPUT
+9.5 VDC SUPPLY
MODULATION INPUT
TCXO MOD INPUT
RX MUTE
MODULATION INPUT
POWER DOWN (I/P)
TO ALL +5 VDC SUPPLY POINTS
PC7 (I/P)
PC6 (I/P)
PC5 (I/P)
PC4 (I/P)
+9.5 VDC SUPPLY
PTT (I/P) A(L)
BOOTSTRAP (I/P)
SW4 COM (O/P)
SW3 COM (O/P)
SW2 COM (O/P)
SW1 COM (O/P)
RX DATA (I/P)
TX DATA (O/P)
PTT CONTROL (O/P)
CHAN SEL0 (I/P)
CHAN SEL2 (I/P)
CHAN SEL3 (I/P)
6K81
R8
1
2
3
BC817
Q8
BC817
Q9
BC817
Q10
27K4
R27
27K4
R34
27K4
R35
27K4
R36
BC817
Q11
27K4
R22
27K4
R37
27K4
R13
100nF
C9
BC817
Q3
27K4
R2
BC817
Q1
BC817
Q2
1
2
3
BC817
Q4
BC817
Q5
BC817
Q6
ENB
CLK
DIN
LOCK
DIN
PWCTL
OUTPUT
SENSE
5VTAP
FB
INPUT
ERROR
SHDN
GND
1
2
6
7
4
3
5
8
U2
LP2951
P
2-
2
P
2-
1
P
2-
6
P2-3
P1-1
P2-4
P1-9
P1-17
VSS
MODA
AS
E
R/W
EXTAL
XTAL
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
RESET
XIRQ
IRQ
PD5
PD4
PD3
PD2
PD1
PD0
VDD
MODB
VRH
PE7
PE6
PE5
PE4
PE3
PE2
PE1
PE0
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
VRL
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
17
18
19
25
24
23
22
21
20
26
34
33
32
31
30
29
28
27
42
41
40
39
38
37
36
35
43
45
47
49
44
46
48
50
51
52
68HC711E9
U4
D1
D1
D2
D2
S1
G1
S2
G2
1
2
3
4
5
6
7
8
SI9933DY
U1
P1-12
P1-19
P1-11
P1-5
P1-13
P1-6
P1-14
P1-15
P1-8
P1-16
R14
27K4
R16
27K4
27K4
R17
DGND
DGND
DGND
DGND
DGND
DGND
DGND
DGND
DGND
DGND
DGND
DGND
DGND
DGND
DGND
DGND
DGND
DGND
DGND
DGND
DGND
+5VD
+5VD
+5VD
+5VD
R15
27K4
+5VD
+5VD
+5VD
+5VD
+5VD
+5VD
DGND
+5VD
+5VD
DGND
DGND
P1-4
27K4
R5
27K4
R3
0R0
R1
27K4
R6
27K4
R4
10K0
R23
10K0
R24
10K0
R25
10K0
R26
215R
R32
215R
R31
215R
R30
P1-1
P1-2
P1-4
P1-5
P1-6
P1-8
P1-9
P1-11
P1-12
P1-13
P1-14
P1-16
P1-17
P1-18
P1-19
P1-20
P1-15
C1
100nF
C2
100nF
27K4
R12
27K4
R18
27K4
R19
27K4
R20
+
4.7uF
C8
+
47uF
C5
TP1
+
47uF
C4
IN
GND
RESET
1
2
4
MC33064
U3
DGND
10.0uH
L1
+
47uF
C3
DGND
P1-20
+5VD
P1-12B
1
2
3
4
5
6
P2
1
J2
1
J1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
P1
P
1-
12
B
DGND
LOCK
CLK
ENB
R21
27K4
DGND
R29
27K4
R9
27K4
R28
27K4
27K4
R7
R10
27K4
2
1
8.0 Mhz
X1
R11
10M0
DGND
P2-1
P2-2
P2-3
P2-4
P2-6
1
J3
P1-18
C7
22pF
TP2
P1-2
DGND
DGND
R33
332R
1
J4
+5VD
27K4
R39
+5VD
DGND
PWCTL
DGND
BC817
Q7
DGND
C11
100nF
C10
100nF
DGND
C6
22pF
BAS16
D1
BAS16
D2
BAS16
D3
BAS16
D4
+5VD
JU2
DGND
221K0
R41
10uF
C15
DGND
JU1
1
2
3
OP140A
U8
DGND
1
2
3
OP140A
U7
DGND
1
2
3
OP140A
U6
DGND
VCC
OUT
GND
1
2
3
4
U9
OPL550
DGND
1K00
R42
TP4
TP5
TP6
TP7
27K4
R40
DGND
C14
100nF
C13
100nF
C12
100nF
1
2
3
OP140A
U5
DGND
TP3
DGND
DGND DGND
+5VD
+5VD
+5VD
R38
27K4
P1-17
OS(R/T)-3H 29-71.4MHZ DIGITAL BOARD SCHEMATIC DIAGRAM
Содержание OSR-3H061
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