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DS80C390 Dual CAN High-Speed Microprocessor 

 

 

5 of 54 

MOVX CHARACTERISTICS (MULTIPLEXED ADDRESS/DATA BUS) (Note 12) 

PARAMETER SYMBOL MIN 

MAX UNITS 

STRETCH 

VALUES 

C

ST

 (MD2:0) 

0.375 t

MCS

 - 5 

 

ns 

C

ST

 = 0 

0.5 t

MCS 

- 5 

 

ns 

1 

£

 C

ST

 

£

 3 

MOVX ALE Pulse Width 

t

LHLL2

 

1.5 t

MCS 

- 10 

 

ns 

4 

£

 C

ST

 

£

 7 

0.125 t

MCS

 - 5 

 

ns 

C

ST

 = 0 

0.25t

MCS 

- 5 

 

ns 

1

£

 C

ST

 

£

 3 

Port 0 MOVX Address, 

CE0–4

, 

PCE0–4

 Valid to ALE Low 

t

AVLL2

 

1.25 t

MCS 

- 10 

 

ns 

4 

£

 C

ST

 

£

 7 

0.25t

MCS

-5  

ns 

C

ST

 = 0 

0.125 t

MCS

 - 5 

 

ns 

1

£

 C

ST

 

£

 3 

Address Hold After MOVX 
Read/Write 

t

LLAX2 

t

LLAX3

 

1.25 t

MCS 

- 5 

 

ns 

4 

£

 C

ST

 

£

 7 

0.5 t

MCS 

- 6 

 

ns 

C

ST

 = 0 

RD

 Pulse Width 

t

RLRH

 

C

ST

 x t

MCS

 - 10 

 

ns 

1 

£

 C

ST

 

£

 7 

0.5 t

MCS 

- 6 

 

ns 

C

ST

 = 0 

WR

 Pulse Width 

t

WLWH

 

C

ST

 x t

MCS

 - 10 

 

ns 

1 

£

 C

ST

 

£

 7 

 0.5 

t

MCS 

- 20 

ns 

C

ST

 = 0 

RD

 Low to Valid Data In 

t

RLDV

 

 

C

ST

 x t

MCS

 - 25 

ns 

1 

£

 C

ST

 

£

 7 

Data Hold After Read 

t

RHDX

 0 

  ns 

 

 0.25 

t

MCS

 - 5 

ns 

C

ST

 = 0 

 0.5t

MCS 

- 5 

ns 

1 

£

 C

ST

 

£

 3 

Data Float After Read 

t

RHDZ

 

 1.5 

t

MCS 

- 5 

ns 

4 

£

 C

ST

 

£

 7 

 0.625 

t

MCS

 - 20 

ns 

C

ST

 = 0 

 (C

ST

 + 0.25) x t

MCS

 - 20 

ns 

1 

£

 C

ST

 

£

 3 

ALE Low to Valid Data In 

t

LLDV

 

 (C

ST

 + 1.25) x t

MCS

 - 20 

ns 

4 

£

 C

ST

 

£

 7 

 0.75 

t

MCS

 - 26 

ns 

C

ST

 = 0 

 (4C

ST

 + 0.5) x t

MCS

 - 30 

ns 

1

£

 C

ST

 

£

 3 

Port 0 Address, Port 4 CE, Port 5 
PCE to Valid Data In 

t

AVDV1

 

 (4C

ST

 + 2.5) x t

MCS

 - 30 

ns 

4 

£

 C

ST

 

£

 7 

 0.75 

t

MCS

 - 30 

ns 

C

ST

 = 0 

 (4C

ST

 + 0.5) x t

MCS

 - 30 

ns 

1 

£

 C

ST

 

£

 3 

Port 2, 4 Address to Valid Data In 

t

AVDV2

 

 (4C

ST

 + 2.5) x t

MCS

 - 30 

ns 

4 

£

 C

ST

 

£

 7 

0.125 t

MCS

 - 5 

0.125 t

MCS

 + 10 

ns 

C

ST

 =0 

0.25t

MCS 

- 5 

0.25t

MCS 

+ 10 

ns 

1 

£

 C

ST

 

£

 3 

ALE Low to 

RD

 or 

WR

 Low 

t

LLWL

 

1.25 t

MCS 

- 5 

1.25 t

MCS 

+ 10 

ns 

4 

£

 C

ST

 

£

 7 

0.25 t

MCS

 - 11 

 

ns 

C

ST

 = 0 

0.5t

MCS 

- 11 

 

ns 

1 

£

 C

ST

 

£

 3 

Port 0 Address, Port 4 CE, Port 5 
PCE to 

RD

 or 

WR

 Low 

t

AVWL1

 

2.5 t

MCS 

- 11 

 

ns 

4 

£

 C

ST

 

£

 7 

0.375 t

MCS

 - 11 

 

ns 

C

ST

 = 0 

0.625t

MCS 

- 11 

 

ns 

1 

£

 C

ST

 

£

 3 

Port 2, 4 Address to or 

WR

 Low 

t

AVWL2

 

2.625 t

MCS 

- 11 

 

ns 

4 

£

 C

ST

 

£

 7 

Data Valid to 

WR

 Transition 

t

QVWX

 -8 

  ns 

 

0.25 t

MCS

 - 8 

 

ns 

C

ST

 = 0 

0.5t

MCS 

- 10 

 

ns 

1 

£

 C

ST

 

£

 3 

Data Hold After 

WR

 High 

t

WHQX

 

1.5 t

MCS 

- 10 

 

ns 

4 

£

 C

ST

 

£

 7 

RD

 Low to Address Float 

t

RLAZ

 

 

See Note 12 

 

 

-5 +10 

ns 

C

ST

 = 0 

0.25 t

MCS

 - 7 

0.25 t

MCS

 + 5 

ns 

1 

£

 C

ST

 

£

 3 

RD

 or 

WR

 High to ALE, Port 4 CE 

or Port 5 PCE High 

t

WHLH

 

1.25 t

MCS 

- 7 

1.25 t

MCS 

+10 ns 

4 

£

 C

ST

 

£

 7 

 

Note 12: 

 

All parameters apply to both commercial and industrial temperature operation. C

ST

 is the stretch cycle value determined by the 

MD2:0 bits. t

MCS

 is a time period shown in the 

t

MCS

 Time Periods

 table. All signals characterized with load capacitance of 80pF 

except Port 0, ALE, 

PSEN

, 

RD

, and 

WR

 with 100pF. Interfacing to memory devices with float times over 25ns can cause bus 

contention and an increase in operating current. Specifications assume a 50% duty cycle for the oscillator; port 2 and ALE timing 
changes in relation to duty cycle variation. Some AC timing characteristic drawings show the CLK signal, provided to determine the 
relative occurrence of events and not the timing of signals relative to the external clock. During the external addressing mode, weak 
latches maintain the previously driven value from the processor on Port 0 until Port 0 is overdriven by external memory; and on Port 
1, 2 and 4 for one XTAL1 cycle prior to change in output address from Port 1, 2, and 4.

 

Содержание DS80C390

Страница 1: ...Speed Microcontroller User s Guide and High Speed Microcontroller User s Guide DS80C390 Supplement must be used in conjunction with this data sheet Download both at www maxim ic com microcontrollers APPLICATIONS Industrial Controls Agricultural Equipment Factory Automation Gaming Equipment Medical Equipment Automotive Heating Ventilation and Air Conditioning FEATURES 80C52 Compatible High Speed Ar...

Страница 2: ...IL 55 mA Logic 1 to 0 Transition Current for Port 1 3 4 5 Note 9 IT1 650 mA Input Leakage Current for Port 0 Input Mode Only IL 300 300 mA RST Pulldown Resistance RRST 50 170 kW Note 1 Active current measured with 40MHz clock source on XTAL1 VCC RST 5 5V all other pins disconnected Note 2 Idle mode current measured with 40MHz clock source on XTAL1 VCC 5 5V RST EA VSS all other pins disconnected No...

Страница 3: ...75 tMCS 30 ns PSEN Low to Address Float tPLAZ 0 0 ns Note 11 All parameters apply to both commercial and industrial temperature operation unless otherwise noted The value tMCS is a function of the machine cycle clock in terms of the processor s input clock frequency These relationships are described in the Stretch Value Timing table All signals characterized with load capacitance of 80pF except Po...

Страница 4: ...ing list of timing symbols is provided as an aid to understanding the timing diagrams SYMBOL FUNCTION t Time A Address C Clock CE Chip Enable D Input Data H Logic Level High L Logic Level Low I Instruction P PSEN Q Output Data R RD Signal V Valid W WR Signal X No longer a valid logic level Z Tri State Figure 1 Multiplexed External Program Memory Read Cycle ...

Страница 5: ...s 4 CST 7 0 25 tMCS 11 ns CST 0 0 5tMCS 11 ns 1 CST 3 Port 0 Address Port 4 CE Port 5 PCE to RD or WR Low tAVWL1 2 5 tMCS 11 ns 4 CST 7 0 375 tMCS 11 ns CST 0 0 625tMCS 11 ns 1 CST 3 Port 2 4 Address to or WR Low tAVWL2 2 625 tMCS 11 ns 4 CST 7 Data Valid to WR Transition tQVWX 8 ns 0 25 tMCS 8 ns CST 0 0 5tMCS 10 ns 1 CST 3 Data Hold After WR High tWHQX 1 5 tMCS 10 ns 4 CST 7 RD Low to Address Fl...

Страница 6: ...DS80C390 Dual CAN High Speed Microprocessor 6 of 54 Figure 2 Multiplexed 9 Cycle Address Data CE0 3 MOVX Read Write Operation ...

Страница 7: ...DS80C390 Dual CAN High Speed Microprocessor 7 of 54 Figure 3 Multiplexed 9 Cycle Address Data PCE0 3 MOVX Read Write Operation ...

Страница 8: ...DS80C390 Dual CAN High Speed Microprocessor 8 of 54 Figure 4 Multiplexed 2 Cycle Data Memory PCE0 3 Read or Write Figure 5 Multiplexed 2 Cycle Data Memory CE0 3 Read ...

Страница 9: ...DS80C390 Dual CAN High Speed Microprocessor 9 of 54 Figure 6 Multiplexed 2 Cycle Data Memory CE0 3 Write Figure 7 Multiplexed 3 Cycle Data Memory PCE0 3 Read or Write ...

Страница 10: ...DS80C390 Dual CAN High Speed Microprocessor 10 of 54 Figure 8 Multiplexed 3 Cycle Data Memory CE0 3 Read Figure 9 Multiplexed 3 Cycle Data Memory CE0 3 Write ...

Страница 11: ...DS80C390 Dual CAN High Speed Microprocessor 11 of 54 Figure 10 Multiplexed 9 Cycle Data Memory PEC0 3 Read or Write Figure 11 Multiplexed 9 Cycle Data Memory CE0 3 Read ...

Страница 12: ...DS80C390 Dual CAN High Speed Microprocessor 12 of 54 Figure 12 Multiplexed 9 Cycle Data Memory CE0 3 Write ...

Страница 13: ...ration unless otherwise noted The value tMCS is a function of the machine cycle clock in terms of the processor s input clock frequency These relationships are described in the Stretch Value Timing table All signals characterized with load capacitance of 80pF except Port 0 ALE PSEN RD and WR with 100pF Interfacing to memory devices with float times turn off times over 25ns can cause bus contention...

Страница 14: ...CS 30 1 CST 3 Port 1 Address Port 4 CE Port 5 PCE to Valid Data In tAVDV1 4CST 2 5 x tMCS 30 ns 4 CST 7 0 75 tMCS 30 CST 0 4CST 0 625 x tMCS 30 1 CST 3 Port 2 4 Address to Valid Data In tAVDV2 4CST 2 625 x tMCS 30 ns 4 CST 7 0 25 tMCS 11 CST 0 0 5 tMCS 11 1 CST 3 Port 0 Address Port 4 CE Port 5 PCE to RD or WR Low tAVWL1 2 5 tMCS 11 ns 4 CST 7 0 375 tMCS 11 CST 0 0 625tMCS 11 1 CST 3 Port 2 4 Addr...

Страница 15: ...DS80C390 Dual CAN High Speed Microprocessor 15 of 54 Figure 14 Nonmultiplexed 9 Cycle Address Data CE0 3 MOVX Read Write Operation ...

Страница 16: ...DS80C390 Dual CAN High Speed Microprocessor 16 of 54 Figure 15 Nonmultiplexed 9 Cycle Address Data PCE0 3 MOVX Read Write Operation ...

Страница 17: ...DS80C390 Dual CAN High Speed Microprocessor 17 of 54 Figure 16 Nonmultiplexed 2 Cycle Data Memory 3 PCE0 Read or Write Figure 17 Nonmultiplexed 2 Cycle Data Memory CE0 3 Read ...

Страница 18: ...DS80C390 Dual CAN High Speed Microprocessor 18 of 54 Figure 18 Nonmultiplexed 2 Cycle Data Memory CE0 3 Write Figure 19 Nonmultiplexed 3 Cycle Data Memory PEC0 3 Read or Write ...

Страница 19: ...DS80C390 Dual CAN High Speed Microprocessor 19 of 54 Figure 20 Nonmultiplexed 3 Cycle Data Memory CE0 3 Read Figure 21 Nonmultiplexed 3 Cycle Data Memory CE0 3 Write ...

Страница 20: ...DS80C390 Dual CAN High Speed Microprocessor 20 of 54 Figure 22 Nonmultiplexed 9 Cycle Data Memory PCE0 3 Read or Write Figure 23 Nonmultiplexed 9 Cycle Data Memory CE0 3 Read ...

Страница 21: ...S TIME PERIODS SYSTEM CLOCK SELECTION 4X 2X CD1 CD0 tMCS 1 0 0 1 tCLCL 0 0 0 2 tCLCL X 1 0 4 tCLCL X 1 1 1024 tCLCL EXTERNAL CLOCK CHARACTERISTICS PARAMETER SYMBOL MIN MAX UNITS Clock High Time tCHCX 8 ns Clock Low Time tCLCX 8 ns Clock Rise Time tCLCH 4 ns Clock Fall Time tCHCL 4 ns Figure 25 External Clock Drive ...

Страница 22: ...s SM2 0 12 clocks per cycle 10 tCLCL Output Data Setup to Clock Rising tQVXH SM2 1 4 clocks per cycle 3 tCLCL ns M2 0 12 clocks per cycle 2 tCLCL Output Data Hold from Clock Rising tXHQX SM2 1 4 clocks per cycle tCLCL ns SM2 0 12 clocks per cycle tCLCL Input Data Hold After Clock Rising tXHDX SM2 1 4 clocks per cycle 0 ns SM2 0 12 clocks per cycle 11 tCLCL Clock Rising Edge to Input Data Valid tXH...

Страница 23: ...DS80C390 Dual CAN High Speed Microprocessor 23 of 54 Figure 26 Serial Port 0 Synchronous Mode HIGH SPEED OPERATION TXD CLK XTAL 4 SM2 1 TRADITIONAL 8051 OPERATION TXD CLOCK XTAL 12 SM2 0 ...

Страница 24: ...536 tCLCL Note 14 Startup time for crystals varies with load capacitance and manufacturer Time shown is for an 11 0592MHz crystal manufactured by Fox Electronics Note 15 Reset delay is a synchronous counter of crystal oscillations during crystal startup Counting begins when the level on the XTAL1 input meets the VIH2 criteria At 40MHz this time is approximately 1 64ms Figure 27 Power Cycle Timing ...

Страница 25: ...t The RST input pin contains a Schmitt voltage input to recognize external active high reset inputs The pin also employs an internal pulldown resistor to allow for a combination of wired OR external reset sources An RC circuit is not required for power up as the device provides this function internally 3 12 RSTOL Reset Output Low Output This active low signal is asserted When the processor has ent...

Страница 26: ... P2 1 37 48 A10 P2 2 38 49 A11 P2 3 39 50 A12 P2 4 42 53 A13 P2 5 43 54 A14 P2 6 44 55 A15 P2 7 A15 A8 Port 2 Output Port 2 serves as the MSB for external addressing The port automatically asserts the address MSB during external ROM and RAM access Although the Port 2 SFR exists the SFR value never appears on the pins due to memory access Therefore accessing the Port 2 SFR is only useful for MOVX A...

Страница 27: ...8 Program Data Memory Address 18 27 37 P4 7 A19 Program Data Memory Address 19 21 14 31 27 25 23 P5 0 P5 7 Port 5 I O Port 5 can function as an 8 bit bidirectional I O port the CAN interface or as peripheral enable signals Setting the SP1EC bit will relocate the RXD1 and TXD1 functions to P5 3 P5 2 as described in the High Speed Microcontroller User s Guide DS80C390 Supplement The reset condition ...

Страница 28: ...DS80C390 Dual CAN High Speed Microprocessor 28 of 54 Figure 28 Block Diagram DS80C390 ...

Страница 29: ...ial port and four 8 bit I O ports plus two 8 bit ports dedicated to memory interfacing are included in the DS80C390 In addition it includes a second hardware serial port seven additional interrupts programmable watchdog timer brownout monitor power fail reset and a programmable output clock that supports an IrDA interface The device provides dual data pointers with increment decrement features to ...

Страница 30: ...combination of instructions These architecture improvements and the submicron CMOS design produce a peak instruction cycle in 100ns 10 MIPS The dual data pointer feature also allows the user to eliminate wasted instructions when moving blocks of memory INSTRUCTION SET SUMMARY All instructions perform exactly the same functions as their 8051 counterparts Their effect on bits flags and other status ...

Страница 31: ... P5CNT CAN1BA CAN0BA SP1EC C1_I O C0_I O P5CNT 2 P5CNT 1 P5CNT 0 A2h C0C ERIE STIE PDE SIESTA CRST AUTOB ERCS SWINT A3h C0S BSS EC96 128 WKS RXS TXS ER2 ER1 ER0 A4h C0IR INTIN7 INTIN6 INTIN5 INTIN4 INTIN3 INTIN2 INTIN1 INTIN0 A5h C0TE A6h C0RE A7h IE EA ES1 ET2 ES0 ET1 EX1 ET0 EX0 A8h SADDR0 A9h SADDR1 AAh C0M1C MSRDY ETI ERI INTRQ EXTRQ MTRQ ROW TIH DTUP ABh C0M2C MSRDY ETI ERI INTRQ EXTRQ MTRQ R...

Страница 32: ...RCS SWINT E3h C1S BSS CECE WKS RXS TXS ER2 ER1 ER0 E4h C1IR INTIN7 INTIN6 INTIN5 INTIN4 INTIN3 INTIN2 INTIN1 INTIN0 E5h C1TE E6h C1RE E7h EIE CANBIE C0IE C1IE EWDI EX5 EX4 EX3 EX2 E8h MXAX EAh C1M1C MSRDY ETI ERI INTRQ EXTRQ MTRQ ROW TIH DTUP EBh C1M2C MSRDY ETI ERI INTRQ EXTRQ MTRQ ROW TIH DTUP ECh C1M3C MSRDY ETI ERI INTRQ EXTRQ MTRQ ROW TIH DTUP EDh C1M4C MSRDY ETI ERI INTRQ EXTRQ MTRQ ROW TIH ...

Страница 33: ... to clear the MST bit to restart the math accelerator state machine Consult the description of the MCNT0 SFR for details of how the shift and normalize functions operate Table 3 Arithmetic Accelerator Sequencing DIVIDE 32 16 OR 16 16 MULTIPLY 16 X 16 Load MA with dividend LSB Load MA with dividend LSB 1 Load MA with dividend LSB 2 Load MA with dividend MSB Load MB with divisor LSB Load MB with div...

Страница 34: ...crocontroller family A device operating in this mode can access up to 64kB of program and data memory The device defaults to this mode following any reset 22 Bit Paged Address Mode The 22 bit paged address mode retains binary code compatibility with the 8051 instruction set but adds one machine cycle to the ACALL LCALL RET and RETI instructions with respect to Dallas Semiconductor s High Speed Mic...

Страница 35: ...Fh 0 1 1 000000h 000FFFh 401000h 4011FFh 1 0 0 400000h 400FFFh 00EE00h 00EFFFh 1 0 1 400000h 400FFFh 401000h 4011FFh 1 1 0 00EE00h 00EFFFh 400000h 400FFFh 1 1 1 401000h 4011FFh 400000h 400FFFh 10 bit expanded stack is not available in shared program data memory mode EXTERNAL MEMORY ADDRESSING The enabling and mapping of the chip enable signals is done through the Port 4 control register P4CNT 92h ...

Страница 36: ... is no way to slow the accesses to program memory other than to use a slower crystal or external clock External MOVX timing is governed by the selection of 0 to 7 stretch cycles controlled by the MD2 MD0 SFR bits in the clock control register CKCON 2 0 A stretch of zero results in a 2 machine cycle MOVX instruction A stretch of seven results in a MOVX of 12 machine cycles Software can dynamically ...

Страница 37: ...TR1 designed to improve performance in applications that require high data throughput Incorporating a second data pointer allows the software to greatly speed up block data MOVX moves by using one data pointer as a source register and the other as the destination register DPTR0 is located at the same address as the original 8051 data pointer allowing the DS80C390 to execute standard 8051 code with...

Страница 38: ...ously provides maximum timing flexibility and maximum availability and economy in crystal selection The logical operation of the system clock divide control function is shown in Figure 29 A 3 1 multiplexer controlled by CD1 CD0 PMR 7 6 selects one of three sources for the internal system clock Crystal oscillator or external clock source Crystal oscillator or external clock source divided by 256 Cr...

Страница 39: ...is order although it is possible to have other instructions between them Any deviation from this order will cause the CD1 CD0 bits to remain unchanged Switching from frequency multiplier to non multiplier mode requires no steps other than the changing of the CD1 CD0 bits 1 Ensure that the CD1 CD0 bits are set to 10 and the RGMD EXIF 2 bit 0 2 Clear the CTM Crystal Multiplier Enable bit 3 Set the 4...

Страница 40: ...ect baud rate in time for a proper serial reception or transmission So with switchback enabled and a serial port enabled the automatic switch to divide by 4 operation occurs in time to receive or transmit a complete serial character as if nothing special had happened STATUS The status register STATUS C5h provides information about interrupt and serial port activity to assist in determining if it i...

Страница 41: ...set or interrupt while in stop mode the bandgap can remain disabled Only the most power sensitive applications should disable the bandgap reference in stop mode as this results in an uncontrolled power down condition RING OSCILLATOR The second enhancement to Stop mode reduces power consumption and allows the device to restart instantly when exiting stop mode The ring oscillator is an internal cloc...

Страница 42: ... COD0 CAN Clock Output Divide Bit 1 and Bit 0 COR 0 CLKOE CAN Clock Output Enable EMI REDUCTION One of the major contributors to radiated noise in an 8051 based system is the toggling of ALE The microcontroller allows software to disable ALE when not used by setting the ALEOFF PMR 2 bit to 1 When ALEOFF 1 ALE automatically toggles during an off chip MOVX However ALE remains static when performing ...

Страница 43: ...rupt flag 512 clocks before setting the reset flag Software can optionally enable this interrupt source which is independent of the watchdog reset function The interrupt is commonly used during the debug process to determine where watchdog reset commands must be located in the application software The interrupt also can serve as a convenient time base generator or can wake up the processor from po...

Страница 44: ... is independent of the interrupt enable and must be cleared by software EXTERNAL RESET PINS The DS80C390 has reset input RST and reset output RSTOL pins The RSTOL pin supplies an active low reset when the microprocessor is issued a reset from either a high on the RST pin a timeout of the watchdog timer a crystal oscillator fail or an internally detected power fail The timing of the RSTOL pin is de...

Страница 45: ...ontrollers that are fully compliant with the CAN 2 0B specification CAN is a highly robust high performance communication protocol for serial communications Popular in a wide range of applications including automotive medical heating ventilation and industrial control the CAN architecture allows for the construction of sophisticated networks with a minimum of external hardware The CAN controllers ...

Страница 46: ...These registers are located in the MOVX memory map 2 A format register C0MxF and C1MxF that informs the CAN processor as to the direction transmit or receive the number of data bytes in the message the identification format standard or extended and the optional use of the identification mask or media mask during message evaluation This register is located in the MOVX memory map 3 Eight data bytes ...

Страница 47: ...X ST MEME MDME xxxx16h C0M1D0 7 CAN 0 MESSAGE 1 DATA BYTES 0 7 xxxx17h 1Eh Reserved xxxx1Fh CAN 0 MESSAGE CENTERS 2 14 MESSAGE CENTER 2 REGISTERS similar to Message Center 1 xxxx20h 2Fh MESSAGE CENTER 3 REGISTERS similar to Message Center 1 xxxx30h 3Fh MESSAGE CENTER 4 REGISTERS similar to Message Center 1 xxxx40h 4Fh MESSAGE CENTER 5 REGISTERS similar to Message Center 1 xxxx50h 5Fh MESSAGE CENTE...

Страница 48: ...X ST MEME MDME xxxx16h C1M1D0 7 CAN 1 MESSAGE 1 DATA BYTES 0 7 xxxx17h 1Eh Reserved xxxx1Fh CAN 1 MESSAGE CENTERS 2 14 MESSAGE CENTER 2 REGISTERS similar to Message Center 1 xxxx20h 2Fh MESSAGE CENTER 3 REGISTERS similar to Message Center 1 xxxx30h 3Fh MESSAGE CENTER 4 REGISTERS similar to Message Center 1 xxxx40h 4Fh MESSAGE CENTER 5 REGISTERS similar to Message Center 1 xxxx50h 5Fh MESSAGE CENTE...

Страница 49: ...ther than an exact match between all bits in the identification field and arbitration values Each CAN processor also incorporates a set of five masks to allow messages with different IDs to be grouped and successfully loaded into a message center Note that some of these masks are optional as per the bits shown in the Arbitration Masking Feature Summary table Table 14 There are several possible arb...

Страница 50: ...ister bank MOVX memory Media ID Mask Registers 0 1 Located in each CAN Control Status Mask Register bank MOVX memory MDME 0 Media byte arbitration disabled MDME 1 Only bits corresponding to 1 in Media ID mask register are compared between data bytes 1 and 2 and Media arbitration registers Message Center 15 Standard 11 Bit Arbitration CAN 2 0A Message Center 15 Arbitration Registers 0 1 Located in ...

Страница 51: ...memory location untouched ERROR COUNTER INTERRUPT GENERATION Each CAN module can be independently configured to alert the microprocessor when either 96 or 128 errors have been detected by the transmit or receive error counters The error count select bit ERCS C0C 1 or C1C 1 selects whether the limit is 96 ERCS 0 or 128 ERCS 1 errors When the error limit is exceeded the CAN error count exceeded bit ...

Страница 52: ...3 specification identical to tLLAX2 Clarified that tRLAZ is held weak latch until overdriven by external memory Removed tPXIZ tPHAV tPHWL and tPHRL from nonmultiplexed address data bus table Corrected PSEN trace in Figure 10 to not show assertion during MOVX write Corrected Table 3 to show unnecessary steps during 16 16 divide Supplied approximate oscillator fail detection frequency Removed text r...

Страница 53: ...gh Speed Microprocessor 53 of 54 PACKAGE INFORMATION The package drawing s in this data sheet may not reflect the most current specifications For the latest package outline information go to www maxim ic com DallasPackInfo ...

Страница 54: ...itry and specifications without notice at any time Maxim Integrated Products 120 San Gabriel Drive Sunnyvale CA 94086 408 737 7600 2005 Maxim Integrated Products Printed USA The Maxim logo is a registered trademark of Maxim Integrated Products Inc The Dallas logo is a registered trademark of Dallas Semiconductor Corp PACKAGE INFORMATION continued The package drawing s in this data sheet may not re...

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