Dallas DS1821, Руководство пользователя

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DS1821
13 of 18
Figure 9 illustrates that the sum of T
INIT
, T
RC
, and T
SAMPLE
must be less than 15
μ
s for a read time slot.
Figure 10 shows that system timing margin is maximized by keeping T
INIT
and T
RC
as short as possible
and by locating the master sample time during read time slots towards the end of the 15
μ
s period.
READ/WRITE TIME SLOT TIMING DIAGRAM
Figure 8
DETAILED MASTER READ 1 TIMING
Figure 9
RECOMMENDED MASTER READ 1 TIMING
Figure 10
V
DD
GND
1-WIRE BUS
15
μ
s
VIH of Master
T
RC
T
INT
> 1
μ
s Master samples
V
DD
GND
1-WIRE BUS
15
μ
s
VIH of Master
T
RC
=
small
T
INT
=
small
Master samples
LINE TYPE LEGEND (Figure 8, Figure 9 and Figure 10)
Bus master pulling low DS1821 pulling low
Resistor pullup
45
μ
s
15
μ
s
V
DD
GND
1-WIRE BUS
60
μ
s < T
X
“0” < 120
1
μ
s < T
REC
<
∞
DS1821 samples
MIN TYP MAX
15
μ
s
30
μ
s
> 1
μ
s
MASTER WRITE “0” SLOT MASTER WRITE “1” SLOT
DS1821 samples
MIN TYP MAX
V
DD
GND
1-WIRE BUS
15
μ
s
MASTER READ “0” SLOT MASTER READ “1” SLOT
Master samples
Master samples
START
OF SLOT
START
OF SLOT
> 1
μ
s
1
μ
s < T
REC
<
∞
15
μ
s
15
μ
s
30
μ
s
15
μ
s
> 1
μ
s