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DS21354 & DS21554
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TCC1/TCC2/TCC3/TCC4: TRANSMIT CHANNEL CONTROL REGISTER
(Address=A0 to A3 Hex)
(MSB)
(LSB)
CH8
CH7
CH6
CH5
CH4
CH3
CH2
CH1
TCC1 (A0)
CH16
CH15
CH14
CH13
CH12
CH11
CH10
CH9
TCC2 (A1)
CH24
CH23
CH22
CH21
CH20
CH19
CH18
CH17
TCC3 (A2)
CH32
CH31
CH30
CH29
CH28
CH27
CH26
CH25
TCC4 (A3)
SYMBOL
POSITION
NAME AND DESCRIPTION
CH 1 - 32
TCC1.0 - 4.7
Transmit Channel Code Insertion Control Bits
0 = do not insert data from the TC register into the transmit data stream
1 = insert data from the TC register into the transmit data stream
11.2 Receive Side Code Generation
On the receive side, the Receive Channel Control Registers (RCC1/2/3/4) are used to determine which of
the 32 E1 channels off of the E1 line and going to the backplane should be overwritten with the code
placed in the Receive Channel Registers (RC1 to RC32). This method allows a different 8–bit code to be
placed into each of the 32 E1 channels.
RC1 TO RC32: RECEIVE CHANNEL REGISTERS
(Address = 80 to 9F Hex)
(for brevity, only channel one is shown; see Table 5-1 for other register address)
(MSB)
(LSB)
C7
C6
C5
C4
C3
C2
C1
C0
RC1 (80)
SYMBOL
POSITION
NAME AND DESCRIPTION
C7
RC1.7
MSB of the Code (this bit is sent first to the backplane)
C0
RC1.0
LSB of the Code (this bit is sent last to the backplane)
RCC1/RCC2/RCC3/RCC4: RECEIVE CHANNEL CONTROL REGISTER
(Address = A4 to A7 Hex)
(MSB)
(LSB)
CH8
CH7
CH6
CH5
CH4
CH3
CH2
CH1
RCC1 (A4)
CH16
CH15
CH14
CH13
CH12
CH11
CH10
CH9
RCC2 (A5)
CH24
CH23
CH22
CH21
CH20
CH19
CH18
CH17
RCC3 (A6)
CH32
CH31
CH30
CH29
CH28
CH27
CH26
CH25
RCC4 (A7)
SYMBOL
POSITION
NAME AND DESCRIPTION
CH1 - 32
RCC1.0 – 4.7
Receive Channel Code Insertion Control Bits
0 = do not insert data from the RC1 register into the receive data stream
1 = insert data from the RC1 register into the receive data stream
12 CLOCK BLOCKING REGISTERS
The Receive Channel blocking Registers (RCBR1 / RCBR2 / RCBR3 / RCBR4) and the Transmit
Channel Blocking Registers (TCBR1 / TCBR2 / TCBR3 / TCBR4) control RCHBLK and TCHBLK pins
respectively. (The RCHBLK and TCHBLK pins are user programmable outputs that can be forced either
high or low during individual channels). These outputs can be used to block clocks to a USART or LAPD
controller in ISDN–PRI applications.