Daewoo DVDP485, Руководство по обслуживанию

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CT908
PRELIMINARY, SUBJECT TO CHANGE WITHOUT NOTICE CTK CONFIDENTIAL, NO DISCLOSURE
The above information is the exclusive intellectual property of Cheertek Inc. and shall not be disclosed, distributed or reproduced without permission from Cheertek Inc.
Copyright (C) 2003 Cheertek Inc. All Rights Reserved.
4. Pin Description
4.1 System Operation Signals and Power/Ground
Pin name Type Description
OSCI I Clock input. It can be oscillator or crystal input. Frequency is 27MHz.
OSCO O Output terminal for crystal connection. This signal also emulates as VCLK for
digital video pixel clock output
RESET# I System reset, active LOW
EMU I Emulation mode select
EMU =0, normal operation, enable internal
micro-controller,
=1, select emulation mode, disable internal
micro-controller.
GPA[3:0]/PD[7:4] I/O General purpose IO bus A bits[3:0], initial in input state/digital video pixel data
bits[7:4] output; GPA[3:0] by default
VLFM AI MPLL loop filter, connect to a capacitor
VLFA AI APLL loop filter, connect to a capacitor
AVD18 (2) AP 1.8V analog power supply for MPLL and APLL
AVSSP (2) AG Analog ground for MPLL and APLL
VDDP (9) DP 3.3V digital power supply for IO driving buffer
VSSP (9) DG Digital ground for IO driving buffer
VDD (9) DP 1.8V digital power supply for core and IO pre-buffer
VSS (9) DG Digital ground for core and IO pre-buffer
4.2 Micro-controller Interface Signals
Pin name Type Internal uC mode (EMU=0) External uC mode (EMU=1)
ALE I/O Address latch enable output. It is used to latch the
address low byte expressed on port0.
ALE: Address latch enable
input.
PSEN# I/O Program strobe enable output. It is used to strobe code
of the external program memory.
LATS: Low byte address
conveying type select input.
LATS=0, mux with SAD[7:0];
LATS=1, conveyed on
SA[7:0]