Daewoo DUX-21U7DT, Руководство по обслуживанию

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CP-530 Service Manual
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Advanced audio configuration
·
High linearity, wide dynamic range and low distortion.
·
Standby or sleep mode in which the DAC is powered down.
PLLsystem clock generation
·
Integrated low jitter PLL for use in applications in which there is digital audio data present but
the system cannot provide an audio related system clock. This mode is called audio mode
·
The PLL can generate 25648kHz and 38448kHz from a 27MHz input clock. This mode is
called video mode
4.9 CI MAX
4.9.1 Features
Module Interface
·
2 full independent module capability
·
Common Interface Standard compliart
ㆍ
DVB_CI (CENELEC EN-50221)
ㆍ
NRSS-B (SCTE IS-679 Part B)
ㆍ
DAVIC v1.2 (CA0 interface)
·
Memory PCMCIA compliance (R2)
ㆍ
8-bit data access
ㆍ
26-bit address Memory card
·
Attribute Memory access (CIS, Tupple)
·
High speed capability
ㆍ
Up to 20Mbits/s on command interface
ㆍ
Up to 100Mbits/s on Transport Stream
·
Polling and interrupt modes
·
Hot insertion (Automatic and Reset VCC handling)
·
3.3V or 5V I/O buffers
PQFP 128package
·
Universal Control Signal Generator (UCSG)
ㆍ
PC Card control signals generation
ㆍ
Supprots powerPC, ARM, ST20, 68xxx, TMS, LSI 64008, TC81220F,
IDTR3041 host microprocessors
·
12C port
ㆍ
CIMAX
TM
Set-up
ㆍ
Slot selection
ㆍ
Cascade mode management (up to 4 CIMAX
TM
)
·
Chip Select bank and interrupt facilities
·
3.3V or 5V I/O buffers
Digital Video Stream Interface
·
MPEG
Ⅱ
Transport Stream compliant
·
3.3V or 5V I/O buffer for direct interface with FEC and DEMUX ICs