Cypress S6J3200 Series, Руководство пользователя

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CHAPTER 15:12-/10-/8-bit Analog to Digital Converter
S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G 257
3.
Operation of A/D Converter
A/D Converter operates using the successive approximation method with 12-bit or 10-bit or 8-bit
resolution. There is one A/D Conversion Data Register per logical channel which is updated each time the
assigned logical channel is converted. First four logical channels can be configured as multiple
conversion channels or used for A/D Converter calibration.
The range comparator compares the converted values with the configured values in the threshold
registers and accordingly generates an interrupt for "inside range" or "outside range", depending on the
configuration. Any of eight range comparators can be configured for any of 64 logical channels.
A/D Pulse Detection function detects events of desired length and also filters parasitic inverted events.
Each logical channel has a dedicated pulse detection function.
3.1.
A/D Conversion Flow
The basic A/D conversion flow is shown on Figure 3-1.
Figure 3-1 A/D Conversion Flow
The important steps marked on the figure are:
(1) A/D conversion request (trigger) is issued for particular logical channel i and the corresponding trigger
status is set.
(2) Period between the trigger and actual conversion start depends on current A/D Converter state
condition
−
If A/D Converter is in idle (power-down) state (power-down mode is enabled
(ADC12Bn_CTRL.PDDMD = "0")) i.e. there are no trigger status set at the moment the trigger is
issued, it is first waited until the resumption time (configured as A/D converter resumption time
register (ADC12Bn_RT)) elapses. At the end of resumption time, the priority arbiter compares the
priorities of all logical channels with set trigger status and inactive data protection feature. The