Cypress PSoC CY8CTMG20 Series, Техническое справочное руководство

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PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C 73
10. Sleep and Watchdog
This chapter discusses the Sleep and Watchdog operations and their associated registers. For a complete table of the Sleep
and Watchdog registers, refer to the
Summary Table of the Core Registers on page 24 . For a quick reference of all PSoC reg-
isters in address order, refer to the Register Reference chapter on page 187 .
10.1 Architectural Description
Device components that are involved in Sleep and Watchdog operation are the selected 32 kHz clock, the wakeup timer, the
Sleep bit in the CPU_SCR0 register, the sleep circuit (to sequence going into and coming out of sleep), the bandgap refresh
circuit (to periodically refresh the reference voltage during sleep), and the
watchdog timer .
Figure 10-1. Sleep Controller Architecture
Outputs
32 kHz CLK
Control Inputs
OSC_SCR0
CPU_SCR0
Wakeup Timer
Sleep Control Logic
Register Decode Logic
(SLP_CFG, SLP_CFG2,
SLP_CFG3, Internal
Configuration Registers)
Sleep Timer
CPU Hold
Off
IMO
CLK
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