Cypress PSoC CY8CTMG20 Series, Техническое справочное руководство

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PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C 21
Pin Information
1.1.3 CY8CTMG200-32LQXI, CY8CTMG200A-32LQXI, CY8CTST200-32LQXI,
CY8CTST200A-32LQXI, CY8CTMG201-32LQXI, CY8CTMG201A-32LQXI PSoC
32-Pin Part Pinout
Table 1-3. 32-Pin QFN Part Pinout **
Pin
No.
Digit
a
l
Analog
Name Description
CY8CTMG200-32LQXI, CY8CTMG200A-32LQXI,
CY8CTST200-32LQXI, CY8CTST200A-32LQXI,
CY8CTMG201-32LQXI, CY8CTMG201A-32LQXI PSoC
Devices
1 IOH I P0[1] Integrating input
2 IO I P2[7]
3 IO I P2[5] XTAL Out
4 IO I P2[3] XTAL In
5 IO I P2[1]
6 IO I P3[3]
7 IO I P3[1]
8 IOHR I P1[7] I2C SCL, SPI SS
9 IOHR I P1[5] I2C SDA, SPI MISO
10 IOHR I P1[3] SPI CLK
11 IOHR I P1[1] TC CLK*, I2C SCL, SPI MOSI
12 Power Vss Ground pin
13 IOHR I P1[0] TC DATA*, I2C SDA, SPI CLK
14 IOHR I P1[2]
15 IOHR I P1[4] EXTCLK
16 IOHR I P1[6]
17 Input XRES Active high external reset with internal pull down
18 IO I P3[0]
19 IO I P3[2]
20 IO I P2[0]
21 IO I P2[2]
22 IO I P2[4]
23 IO I P2[6]
24 IOH I P0[0]
25 IOH I P0[2]
26 IOH I P0[4]
27 IOH I P0[6]
28 Power Vdd Power pin
29 IOH I P0[7]
30 IOH I P0[5]
31 IOH I P0[3]
32 Power Vss Ground pin
LEGEND
A = Analog, I = Input, O = Output, NC = No Connection, H = 5 mA High Output Drive, R = Regulated Output Option.
* ISSP pin which is not High Z at POR (Power On Reset).
** The center pad on the QFN package must be connected to ground (Vss) for best mechanical, thermal, and electrical performance. If not
connected to ground, it must be electrically floated and not connected to any other signal.
P0[1]
P2[7]
P2[5]
P2[3]
P2[1]
P3[3]
QFN
(Top View)
9
10 11 12
13 14 15 16
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
32 31 30 29 28 27 26 25
Vss
P0
[3
]
P0
[7
]
Vd
d
P0
[6
]
P0
[4
]
P0
[2
]
P3[1]
P1[7]
P0[0]
P2[6]
P3[0]
XRES
P1[5
]
P1[3
]
P1[
1
]
Vs
s
P1[0
]
P1
[2
]
P1[4
]
P1
[6
]
P2[4]
P2[2]
P2[0]
P3[2]
P0
[5
]
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