Document Number: 002-04578 Rev. *A
Page 53 of 64
MB90910 Series
11.4.8 CAN PLL cycle jitter
Parameter
Sym-
bol
Pin
name
Condition
Value
Unit
Remarks
Min
Typ
Max
CAN PLL cycle jitter
(When locked)
t
PJ
10
10
ns
F
CP
16 MHz
(4 MHz multiplied by 4)
24 MHz
(4 MHz multiplied by 6)
32 MHz
(4 MHz multiplied by 8)
t1
t2
t3
t1
t2
t3
tn-1
tn
tn-1
tn
CAN PLL cycle jitter
Deviation time from the ideal clock is assured per cycle out of 20, 000 cycles.
PLL output
Ideal clock
Deviation
time
Slow
Fast