Document No. 002-14949 Rev. *E
Page 44 of 113
PRELIMINARY
CYW43353
9.2.1.1. Command Structure
The gSPI command structure is 32 bits. The bit positions and definitions are as shown in
.
Figure 22. gSPI Command Structure
9.2.1.2. Write
The host puts the first bit of the data onto the bus half a clock-cycle before the first active edge following the CS going low. The fol-
lowing bits are clocked out on the falling edge of the gSPI clock. The device samples the data on the active edge.
9.2.1.3. Write/Read
The host reads on the rising edge of the clock requiring data from the device to be made available before the first rising clock edge
of the clock burst for the data. The last clock edge of the fixed delay word can be used to represent the first bit of the following data
word. This allows data to be ready for the first clock edge without relying on asynchronous delays.
9.2.1.4. Read
The read command always follows a separate write to set up the WLAN device for a read. This command differs from the write/read
command in the following respects: a) chip selects go high between the command/address and the data and b) the time interval
between the command/address is not fixed.
0
10
27
11
P a cket length - 11b its *
Ad dres s – 17 bits
F1
F 0
C
A
F unction N o: 00 – F unc 0
01 – F unc 1
10 – F unc 2
11 – F unc 3
C ommand : 0 – R ead
1 – W rite
28
29
30
31
A cce ss : 0 – F ixed add ress
1 – Incremental add res s
* 11’ h0 = 204 8 by tes
0
10
27
11
P a cket length - 11b its *
Ad dres s – 17 bits
F1
F 0
C
A
F unction N o: 00 – F unc
Ϭ͗ůů^W/ƐƉĞĐŝĮĐƌĞŐŝƐƚĞƌƐ
01 – F unc 1: Registers and meories belonging to other blocks in the chip (64 bytes max)
10 – F unc 2: DMA channel 1. WLAN packets up to 2048 bytes.
11 – F unc
ϯ͗DĐŚĂŶŶĞůϮ;ŽƉƟŽŶĂůͿ͘WĂĐŬĞƚƐƵƉƚŽϮϬϰϴďLJƚĞƐ͘
C ommand : 0 – R ead
1 – W rite
28
29
30
31
A cce ss : 0 – F ixed add ress
1 – Incremental add res s
* 11’ h0 = 204 8 by tes
BCM_SPID Command Structure
