Cypress CYW43353, Руководство пользователя

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Document No. 002-14949 Rev. *E Page 103 of 113
PRELIMINARY
CYW43353
18.1.5 gSPI Signal Timing
The gSPI host and device always use the rising edge of clock to sample data.
Figure 41. gSPI Timing
18.2 JTAG Timing
Table 52. gSPI Timing Parameters
Parameter Symbol Minimum Maximum Units Note
Clock period T1 20.8 – ns F
max
= 48 MHz
Clock high/low T2/T3 (0.45 × T1) – T4 (0.55 × T1) – T4 ns –
Clock rise/fall time
1
1. Limit applies when SPI_CLK = F
max
. For slower clock speeds, longer rise/fall times are acceptable provided that the transitions are monotonic and the
setup and hold time limits are complied with.
T4/T5 – 2.5 ns Measured from 10% to 90% of VDDIO
Input setup time T6 5.0 – ns Setup time, SIMO valid to SPI_CLK active edge
Input hold time T7 5.0 – ns Hold time, SPI_CLK active edge to SIMO invalid
Output setup time T8 5.0 – ns Setup time, SOMI valid before SPI_CLK rising
Output hold time T9 5.0 – ns Hold time, SPI_CLK active edge to SOMI invalid
CSX to clock
2
2. SPI_CSx remains active for entire duration of gSPI read/write/write-read transaction (overall words for multiple-word transaction).
– 7.86 – ns CSX fall to 1st rising edge
Clock to CSX
a
– – – ns Last falling edge to CSX high
Table 53. JTAG Timing Characteristics
Signal Name Period
Output
Maximum
Output
Minimum Setup Hold
TCK 125 ns – – – –
TDI – – – 20 ns 0 ns
TMS – – – 20 ns 0 ns
TDO – 100 ns 0 ns – –
JTAG_TRST 250 ns – – – –