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CY62158EV30 MoBL

®

Document #: 38-05578 Rev. *D

Page 4 of 11

Thermal Resistance

[9]

Parameter

Description

Test Conditions

BGA

TSOP II

Unit

Θ

JA

Thermal Resistance 

(Junction to Ambient)

Still Air, soldered on a 3 x 4.5 inch, 

two-layer printed circuit board

72

76.88

°

C/W

Θ

JC

Thermal Resistance

 

(Junction to Case)

8.86

13.52

°

C/W

AC Test Loads and Waveforms

 

V

CC

 

V

CC

OUTPUT

R2

30 pF

INCLUDING

JIG AND

SCOPE

GND

90%

10%

90%

10%

OUTPUT

V

TH

Equivalent to:

THÉ

 

VENIN EQUIVALENT

ALL INPUT PULSES

R

TH

R1

Fall time: 1 V/ns

Rise Time: 1 V/ns

Parameters

2.5V

 3.0V

Unit

R1

16667

1103

R2

15385

1554

R

TH

8000

645

V

TH

1.20

1.75

V

Data Retention Characteristics

 (Over the Operating Range)

Parameter

Description

Conditions

Min

Typ

[4]

Max

Unit

V

DR

V

CC

 for Data Retention

1.5

V

I

CCDR

[8]

Data Retention Current V

CC

 = 1.5V, CE

1

 > V

CC

 −

 0.2V 

or CE

2

 < 0.2V, V

IN

 > V

CC

 

− 

0.2V 

or V

IN

 < 0.2V

2

5

µ

A

t

CDR

[9]

Chip Deselect to Data 

Retention Time

0

ns

t

R

[10]

Operation Recovery 

Time

t

RC

ns

Data Retention Waveform

V

CC

, min

V

CC

, min

t

CDR

V

DR

 > 1.5V

t

R

CE

1

V

CC

CE

2

 

 

DATA RETENTION MODE

 or

Note

10. Full Device AC operation requires linear V

CC

 ramp from V

DR 

to V

CC(min)

 > 100 

µ

s or stable at V

CC(min)

 > 100 

µ

s.

[+] Feedback 

Содержание CY62158EV30

Страница 1: ...sumption significantly when deselected CE1 HIGH or CE2 LOW The eight input and output pins IO0 through IO7 are placed in a high impedance state when the device is deselected CE1 HIGH or CE2 LOW the outputs are disabled OE HIGH or a write operation is in progress CE1 LOW and CE2 HIGH and WE LOW To write to the device take Chip Enables CE1 LOW and CE2 HIGH and Write Enable WE input LOW Data on the e...

Страница 2: ...13 A12 NC A18 A19 3 2 6 5 4 1 D E B A C F G H A16 VSS NC NC NC NC NC NC NC NC NC NC NC 48 Ball VFBGA WE 1 2 3 4 5 6 7 8 9 10 11 14 31 32 36 35 34 33 37 40 39 38 12 13 41 44 43 42 16 15 29 30 VCC A19 A18 A17 A16 A4 A3 OE VSS A5 NC A2 CE1 IO 0 NC NC CE2 A1 A0 18 17 20 19 IO 1 27 28 25 26 22 21 23 24 VSS NC IO 2 IO 3 NC A6 A7 A8 VCC NC IO 7 IO 6 IO 5 IO 4 NC NC A10 A11 A12 A13 A15 A14 A9 Top View 44 ...

Страница 3: ...o 3 6V 2 2 VCC 0 3V V VIIL Input LOW Voltage VCC 2 2V to 2 7V 0 3 0 6 V VCC 2 7V to 3 6V 0 3 0 8 V IIX Input Leakage Current GND VI VCC 1 1 µA IOZ Output Leakage Current GND VO VCC Output Disabled 1 1 µA ICC VCC OperatingSupplyCurrent f fmax 1 tRC VCC VCCmax IOUT 0 mA CMOS levels 18 25 mA f 1 MHz 1 8 3 mA ISB1 Automatic CE Power down Current CMOS Inputs CE1 VCC 0 2V CE2 0 2V VIN VCC 0 2V VIN 0 2V ...

Страница 4: ...TH R1 Fall time 1 V ns Rise Time 1 V ns Parameters 2 5V 3 0V Unit R1 16667 1103 Ω R2 15385 1554 Ω RTH 8000 645 Ω VTH 1 20 1 75 V Data Retention Characteristics Over the Operating Range Parameter Description Conditions Min Typ 4 Max Unit VDR VCC for Data Retention 1 5 V ICCDR 8 Data Retention Current VCC 1 5V CE1 VCC 0 2V or CE2 0 2V VIN VCC 0 2V or VIN 0 2V 2 5 µA tCDR 9 Chip Deselect to Data Rete...

Страница 5: ...5 ns tSD Data Setup to Write End 25 ns tHD Data Hold from Write End 0 ns tHZWE WE LOW to High Z 12 13 18 ns tLZWE WE HIGH to Low Z 12 10 ns Notes 11 Test conditions for all parameters other than tri state parameters assume signal transition time of 3 ns or less 1V ns timing reference levels of VCC typ 2 input pulse levels of 0 to VCC typ and output loading of the specified IOL IOH as shown in AC T...

Страница 6: ... OUT PREVIOUS DATA VALID DATA VALID tRC tAA tOHA 50 50 DATA VALID tRC tACE tDOE tLZOE tLZCE tPU HIGH IMPEDANCE tHZOE tHZCE tPD HIGH ICC ISB IMPEDANCE OE CE1 ADDRESS CE2 DATA OUT SUPPLY CURRENT VCC Notes 15 Device is continuously selected OE CE1 VIL CE2 VIH 16 WE is HIGH for read cycle 17 Address valid before or similar to CE1 transition LOW and CE2 transition HIGH Feedback ...

Страница 7: ...SA tHA tAW tSCE tWC tHZOE VALID DATA NOTE 20 CE1 ADDRESS CE2 WE DATA IO OE tWC VALID DATA tAW tSA tPWE tHA tHD tSD tSCE CE1 ADDRESS CE2 WE DATA IO OE Notes 18 Data IO is high impedance if OE VIH 19 If CE1 goes HIGH or CE2 goes LOW simultaneously with WE HIGH the output remains in high impedance state 20 During this period the IOs are in output state Do not apply input signals Feedback ...

Страница 8: ...t Read Active ICC L H H H High Z Output Disabled Active ICC L H L X Data in Write Active ICC Ordering Information Speed ns Ordering Code Package Diagram Package Type Operating Range 45 CY62158EV30LL 45BVXI 51 85150 48 ball Very Fine Pitch Ball Grid Array Pb free Industrial CY62158EV30LL 45ZSXI 51 85087 44 pin TSOP II Pb free Switching Waveforms continued VALID DATA tHD tSD tLZWE tPWE tSA tHA tAW t...

Страница 9: ...150 A 1 A1 CORNER 0 75 0 75 Ø0 30 0 05 48X Ø0 25 M C A B Ø0 05 M C B A 0 15 4X 0 21 0 05 1 00 MAX C SEATING PLANE 0 55 MAX 0 25 C 0 10 C A1 CORNER TOP VIEW BOTTOM VIEW 2 3 4 3 75 5 25 B C D E F G H 6 5 4 6 5 2 3 1 D H F G E C B A 6 00 0 10 8 00 0 10 A 8 00 0 10 6 00 0 10 B 1 875 2 625 0 26 MAX 51 85150 D Feedback ...

Страница 10: ...ursuant to an express written agreement with Cypress Furthermore Cypress does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress products in life support systems application implies that the manufacturer assumes all risk of such use and in do...

Страница 11: ... mA to 3 mA for test condition f 1MHz Changed the ISB1 and ISB2 max value from 4 5 µA to 8 µA and Typ value from 0 9 µA to 2 µA respectively Updated Thermal Resistance table Changed Test Load Capacitance from 50 pF to 30 pF Added Typ value for ICCDR Changed the ICCDR max value from 4 5 µA to 5 µA Corrected tR in Data Retention Characteristics from 100 µs to tRC ns Changed tLZOE from 3 to 5 Changed...

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