background image

CY2048WAF

Document #: 38-07738 Rev. *A

Page 2 of 7

Die Pad Summary 

(Pad coordinates are referenced from the center of the die (X = 0, Y = 0))

Name

Pad Number 

Description

X coordinate (

µ

m)

Y coordinate (

µ

m)

VDD

1

Voltage Supply

–360.8

353.7

XOUT

2

Oscillator Drain

–360.8

134.1

XIN

3

Oscillator Gate

–360.8

–42.6

PD#/OE

4

Programmable power-down or output enable pin

–360.8

–275.9

VPP

High voltage for programming NV memory

SDATA

Serial data pin used for programming in test mode

OUT

6

Clock output 

360.0

353.7

SCL

Serial clock for programming in test mode

VSS

5

Ground

360.0

–354.5

[+] Feedback 

Содержание CY2048WAF

Страница 1: ...ne tuning of output clock frequency by adjusting CLoad of the crystal Allows multiple programming opportunities to correct errors and control excess inventory Enables programming of output frequency after packaging PPM clock output error can be adjusted in package Provides flexibility in output configurations and testing Enables low power operation or output enable function Provides flexibility fo...

Страница 2: ...te µm VDD 1 Voltage Supply 360 8 353 7 XOUT 2 Oscillator Drain 360 8 134 1 XIN 3 Oscillator Gate 360 8 42 6 PD OE 4 Programmable power down or output enable pin 360 8 275 9 VPP High voltage for programming NV memory SDATA Serial data pin used for programming in test mode OUT 6 Clock output 360 0 353 7 SCL Serial clock for programming in test mode VSS 5 Ground 360 0 354 5 Feedback ...

Страница 3: ...125 C CXIN Capacitance XIN all tuning caps OFF 10 pF CXOUT Capacitance XOUT all tuning caps OFF 10 pF CL All tuning Caps OFF 4 5 6 pF All tuning Caps ON 9 2 10 11 4 pF COUT Output Load Capacitance 15 pF tRAMP Power up time for VDD to reach minimum specified voltage power ramps must be monotonic 0 05 500 ms TS Start up time 90 VDD to valid frequency on output 10 ms DC Electrical Specifications TJ 4...

Страница 4: ...sured at VDD 2 4 15 ps tPJ2 2 Peak to peak Period Jitter XIN 10 48 MHz Measured at VDD 2 30 80 ps DL Crystal drive level 48 MHz crystal CL 7 pF C0 2 pF R1 10 Ohms Temp 25 C VDD 3 6V 350 400 µW R Negative Resistance Measured at 48 MHz CL 10 pF C0 5 pF 150 Ω FDRIFT Output Frequency Drift 3 0V 10 3 3V 10 for Temp 25 C 2 2 ppm Phase Noise Temp 25 C VDD 3 3V FNOM 10MHz XCAP 7F Hex Offset dBc Hz Typ 10 ...

Страница 5: ...hronous mode 3 ms TPZX SYNC Time from rising edge on OE to running output synchronous mode T 1 Fout 1 5T 350 ns TPZX ASYNC Time from rising edge on OE to running output asynchronous mode 350 ns TPXZ SYNC Time from falling edge on OE to high impedance output synchronous mode T 1 Fout 1 5T 350 ns TPXZ ASYNC Time from falling edge on OE to high impedance output asynchronous mode 350 ns Figure 2 Power...

Страница 6: ...stems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress products in life support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges Voltage and Timing Definitions All product or company names mentioned in this document may be the trademark...

Страница 7: ...ment Title CY2048WAF Flash Programmable Capacitor Tuning Array Die for Crystal Oscillator XO Document Number 38 07738 REV ECN NO Issue Date Orig of Change Description of Change 319840 See ECN RGL New data sheet A 413511 See ECN RGL Minor Change Pls post in the web Feedback ...

Отзывы: