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CY14B101L

Document Number: 001-06400 Rev. *I

Page 11 of 18

AutoStore or Power Up RECALL

Parameter

Alt

Description

CY14B101L

Unit

Min

Max

HRECALL

[13]

RESTORE

Power up RECALL Duration

STORE

[14, 15]

HLHZ

STORE Cycle Duration

12.5

SWITCH

Low Voltage Trigger Level

2.65

VCCRISE

Rise Time

150

Switching Waveforms

Figure 9. AutoStore/Power Up RECALL

SWITCH

STORE

HRECALL

AutoStore

POWER-UP RECALL

Read & Write Inhibited

STORE occurs only
if a SRAM write
has happened

No STORE occurs
without atleast one
SRAM write

VCCRISE

Note

Read and Write cycles are ignored during STORE, RECALL, and while Vcc is below V

SWITCH

Notes

13. t

HRECALL

starts from the time V

rises above V

SWITCH

14. If an SRAM WRITE has not taken place since the last nonvolatile cycle, no STORE will take place.
15. Industrial Grade devices requires 15 ms max.

[+] Feedback

Содержание CY14B101L

Страница 1: ...ypress CY14B101L is a fast static RAM with a nonvolatile element in each memory cell The embedded nonvolatile elements incorporate QuantumTrap technology producing the world s most reliable nonvolatile memory The SRAM provides unlimited read and write cycles while independent nonvolatile data resides in the highly reliable QuantumTrap cell Data transfers from the SRAM to the nonvolatile elements t...

Страница 2: ...Supply Power Supply Inputs to the Device HSB Input or Output Hardware Store Busy HSB When LOW this output indicates a Hardware Store is in progress When pulled low external to the chip it initiates a nonvolatile STORE operation A weak internal pull up resistor keeps this pin high if not connected connection optional VCAP Power Supply AutoStore Capacitor Supplies power to nvSRAM during power loss t...

Страница 3: ...r down AutoStore operation is a unique feature of QuantumTrap technology and is enabled by default on the CY14B101L During normal operation the device draws current from VCC to charge a capacitor connected to the VCAP pin This stored charge is used by the chip to perform a single STORE operation If the voltage on the VCC pin drops below VSWITCH the part automatically disconnects the VCAP pin from ...

Страница 4: ...L cycle the following sequence of CE controlled READ operations is performed 1 Read address 0x4E38 Valid READ 2 Read address 0xB1C7 Valid READ 3 Read address 0x83E0 Valid READ 4 Read address 0x7C1F Valid READ 5 Read address 0x703F Valid READ 6 Read address 0x4C63 Initiate RECALL cycle Internally RECALL is a two step procedure First the SRAM data is cleared and then the nonvolatile information is t...

Страница 5: ...ls in an nvSRAM are programmed on the test floor during final test and quality assurance Incoming inspection routines at customer or contract manufacturer s sites sometimes reprogram these values Final NV patterns are typically repeating patterns of AA 55 00 FF A5 or 5A End product s firmware should not assume an NV array is in a set programmed state Routines that check memory content values to de...

Страница 6: ...Output Data Output Data Output Data Active 1 2 3 L H L 0x4E38 0xB1C7 0x83E0 0x7C1F 0x703F 0x8FC0 Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Nonvolatile Store Output Data Output Data Output Data Output Data Output Data Output High Z Active ICC2 1 2 3 L H L 0x4E38 0xB1C7 0x83E0 0x7C1F 0x703F 0x4C63 Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Nonvolatile Recall Output Data Output Data Ou...

Страница 7: ...ns Dependent on output loading and cycle rate Values obtained without output loads IOUT 0 mA Commercial 65 55 50 mA mA Industrial 70 60 55 mA mA mA ICC2 Average VCC Current during STORE All Inputs Do Not Care VCC Max Average current for duration tSTORE 6 mA ICC3 Average VCC Current at tRC 200 ns 5V 25 C Typical WE VCC 0 2V All other inputs cycling Dependent on output loading and cycle rate Values ...

Страница 8: ...he thermal resistance parameters are listed 6 Parameter Description Test Conditions 32 SOIC 48 SSOP Unit ΘJA Thermal Resistance Junction to Ambient Test conditions follow standard test methods and procedures for measuring thermal impedance per EIA JESD51 33 64 32 9 C W ΘJC Thermal Resistance Junction to Case 13 6 16 35 C W Figure 4 AC Test Loads AC Test Conditions 3 0V Output 30 pF R1 577Ω R2 789Ω...

Страница 9: ...Z Chip Disable to Output Inactive 10 13 15 ns tLZOE 9 tGLQX Output Enable to Output Active 0 0 0 ns tHZOE 9 tGHQZ Output Disable to Output Inactive 10 13 15 ns tPU 6 tELICCH Chip Enable to Power Active 0 0 0 ns tPD 6 tEHICCL Chip Disable to Power Standby 25 35 45 ns Switching Waveforms Figure 5 SRAM Read Cycle 1 Address Controlled 7 8 10 Figure 6 SRAM Read Cycle 2 CE and OE Controlled 7 10 W5 W W2...

Страница 10: ...s Setup to Start of Write 0 0 0 ns tHA tWHAX tEHAX Address Hold After End of Write 0 0 0 ns tHZWE 9 11 tWLQZ Write Enable to Output Disable 10 13 15 ns tLZWE 9 tWHQX Output Active After End of Write 3 3 3 ns Switching Waveforms Figure 7 SRAM Write Cycle 1 WE Controlled 11 12 Figure 8 SRAM Write Cycle 2 CE and OE Controlled 11 12 tWC tSCE tHA tAW tSA tPWE tSD tHD tHZWE tLZWE ADDRESS CE WE DATA IN D...

Страница 11: ...e 9 AutoStore Power Up RECALL V CC V SWITCH tSTORE tSTORE tHRECALL tHRECALL AutoStore POWER UP RECALL Read Write Inhibited STORE occurs only if a SRAM write has happened No STORE occurs without atleast one SRAM write tVCCRISE Note Read and Write cycles are ignored during STORE RECALL and while Vcc is below VSWITCH Notes 13 tHRECALL starts from the time VCC rises above VSWITCH 14 If an SRAM WRITE h...

Страница 12: ... Switching Waveforms Figure 10 CE Controlled Software STORE RECALL Cycle 17 Figure 11 OE Controlled Software STORE RECALL Cycle 17 tRC tRC tSA tSCE tHA tSTORE tRECALL DATA VALID DATA VALID 6 S S E R D D A 1 S S E R D D A HIGH IMPEDANCE ADDRESS CE OE DQ DATA tRC tRC 6 S S E R D D A 1 S S E R D D A ADDRESS tSA tSCE tHA tSTORE tRECALL DATA VALID DATA VALID HIGH IMPEDANCE CE OE DQ DATA Notes 16 The so...

Страница 13: ...13 Soft Sequence Processing 19 20 3 6 GGUHVV GGUHVV GGUHVV GGUHVV 6RIW 6HTXHQFH RPPDQG W66 W66 GGUHVV 9 W6 W 6RIW 6HTXHQFH RPPDQG W Notes 18 On a hardware STORE initiation SRAM operation continues to be enabled for time tDELAY to allow read and write cycles to complete 19 This is the amount of time to take action on a soft sequence command Vcc power must remain high to effectively register command...

Страница 14: ...pin SSOP 35 CY14B101L SZ35XCT 51 85127 32 pin SOIC Commercial CY14B101L SZ35XC 51 85127 32 pin SOIC CY14B101L SP35XCT 51 85061 48 pin SSOP CY14B101L SP35XC 51 85061 48 pin SSOP CY14B101L SZ35XIT 51 85127 32 pin SOIC Industrial CY14B101L SZ35XI 51 85127 32 pin SOIC CY14B101L SP35XIT 51 85061 48 pin SSOP CY14B101L SP35XI 51 85061 48 pin SSOP Option T Tape and Reel Blank Std Speed 25 25 ns 35 35 ns 4...

Страница 15: ...tion Please contact your local Cypress sales representative for availability of these parts Package Diagrams Figure 14 32 Pin 300 Mil SOIC 51 85127 Ordering Information Speed ns Ordering Code Package Diagram Package Type Operating Range 51 85058 A PIN 1 ID SEATING PLANE 1 16 17 32 DIMENSIONS IN INCHES MM MIN MAX 0 292 7 416 0 299 7 594 0 405 10 287 0 419 10 642 0 050 1 270 TYP 0 090 2 286 0 100 2 ...

Страница 16: ...CY14B101L Document Number 001 06400 Rev I Page 16 of 18 Figure 15 48 Pin Shrunk Small Outline Package 51 85061 Package Diagrams continued 51 85061 C Feedback ...

Страница 17: ...the software command Updated Part Nomenclature Table and Ordering Information Table D 597002 TUP Removed VSWITCH min specification from the AutoStore Power Up RECALL table Changed tGLAX specification from 20 ns to 1 ns Added tDELAY max specification of 70 μs in the hardware STORE cycle table Removed tHLBL specification Changed tSS specification from 70 μs min to 70 μs max Changed VCAP max from 57 ...

Страница 18: ...or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement Any reproduction modification translation compilation or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND EXPRESS OR IMPLIED W...

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