Cypress AN94024, Начало работы

Страница: 8 / 13

Getting Started with CY27410/30: 4-PLL Spread-Spectrum Clock Generator
www.cypress.com
Document No. 001-94024 Rev.*A 8
Figure 22. Phase Delay Circuit Example
O1d4
Low
DIVO1
1/2*f
VCO
Sh
if
t
Re
g
is
te
r
O1d2
O1d3
O1d1
O1
O1d4
Low
DIVO2
O1d2
O1d3
O1d1
O1x
O2
O1x
0
1
2
3
4
5
6
0
1
2
3
4
5
6
Figure 23. Phase Delay Timing Diagram
CY27410 supports a maximum of four units (t
DL
) of
delay(s)
Even when you choose the same DIVO (Ox above) value
for O1 and O2 (O3, O4), it does not guarantee phase-
aligned clocks between outputs. To get phase-aligned
outputs, use O1x for other output(s).
Most of the ZDB outputs should use O1x for all outputs.
However, if you intentionally choose delayed output to
provide feedback, you can get the Early (or Late) phase
clocks described below.
Figure 24. Alignment of Delayed Outputs of CY27410
In the example shown in figure 24, one delayed output
(O1d1) is fed back to IN2, while early clock selected is
O1x, and delayed output selected is O1d3.
In CLKGEN mode, you may use this delay circuit to
generate N (x t
DL
) delayed phase clock(s). For applications
that need to adjust some skew or need fixed delay phase,
you may use this function. For example, if trace
characteristics are such that the propagation delay is
175 ps/inch, then a four inch-delay will be 700 ps.
Voltage-Controlled Frequency Shift (VCFS)
CY27410 mimics the VCXO feature found in crystal
oscillators with VCFS. The device modulates the PLL
(VCO) frequency up to 120 ppm. The modulation is
completely programmable. Please see
Figure 26 for the
VCFS shift profile.
Figure 25. VCFS Shift Profile
-200
-150
-100
-50
0
50
100
150
200
250
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2
Atlas VCFS Char
Gain=000 Gain=001 Gain=010 Gain=011
Gain=100 Gain=101 Gain=110 Gain=111
V C F S i n Ap p l i c a t i o n s
For some applications, the output clock frequency should
track incoming data stream by using analog feedback. The
CY27410 device acts as a part of the large phase lock
loop shown in
Figure 26 . The ASIC or SoC tracks the
incoming stream, calculates the error, and generates the
PWM signal (typically), following which the error
information is fed back to the local clock generator
(CY27410) for frequency tuning.
Figure 26. VCFS Example
The VCFS function modifies the PLL frequency, so the
frequency pulling is not dependent on the crystal
characteristic, temperature, voltage, or device process.
The VCFS modulation profile is linear and accurate and
you may use clock reference as well.
CY27410
VCFS plot