Cypress Semiconductor MoBL CY62146ESL Скачать руководство пользователя страница 11 | Manualshive

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CY62146ESL MoBL

®

Document #: 001-43142 Rev. **

Page 11 of 12

Package Diagrams

Figure 8. 44-Pin TSOP II, 51-85087

51-85087-*A

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Содержание MoBL CY62146ESL

Страница 1: ...tput pins IO0 through IO15 are placed in a high impedance state when Deselected CE HIGH Outputs are disabled OE HIGH Both Byte High Enable and Byte Low Enable are disabled BHE BLE HIGH Write operation is active CE LOW and WE LOW To write to the device take Chip Enable CE and Write Enable WE inputs LOW If Byte Low Enable BLE is LOW then data from IO pins IO0 through IO7 is written into the location...

Страница 2: ...32 36 35 34 33 37 40 39 38 12 13 41 44 43 42 16 15 29 30 A5 18 17 20 19 27 28 25 26 22 21 23 24 A6 A7 A4 A3 A2 A1 A0 A15 A16 A8 A9 A10 A11 A13 A14 A12 OE BHE BLE CE WE IO0 IO1 IO2 IO3 IO4 IO5 IO6 IO7 IO8 IO9 IO10 IO11 IO12 IO13 IO14 IO15 VCC VCC VSS VSS NC 10 A17 Notes 1 NC pins are not connected on the die 2 Datasheet specifications are not guaranteed for VCC in the range of 3 6V to 4 5V 3 Typica...

Страница 3: ...4 4 5 VCC 5 5 IOH 1 0 mA 2 4 VOL Output LOW Voltage 2 2 VCC 2 7 IOL 0 1 mA 0 4 V 2 7 VCC 3 6 IOL 2 1mA 0 4 4 5 VCC 5 5 IOL 2 1mA 0 4 VIH Input HIGH Voltage 2 2 VCC 2 7 1 8 VCC 0 3 V 2 7 VCC 3 6 2 2 VCC 0 3 4 5 VCC 5 5 2 2 VCC 0 5 VIL Input LOW Voltage 2 2 VCC 2 7 0 3 0 6 V 2 7 VCC 3 6 0 3 0 8 4 5 VCC 5 5 0 5 0 8 IIX Input Leakage Current GND VI VCC 1 1 μA IOZ Output Leakage Current GND VO VCC Outp...

Страница 4: ... may affect these parameters Parameter Description Test Conditions TSOP II Unit ΘJA Thermal Resistance Junction to Ambient Still Air soldered on a 3 4 5 inch two layer printed circuit board 77 C W ΘJC Thermal Resistance Junction to Case 13 C W AC Test Loads and Waveforms Parameters 2 5V 3 0V 5 0V Unit R1 16667 1103 1800 Ω R2 15385 1554 990 Ω RTH 8000 645 639 Ω VTH 1 20 1 75 1 77 V VCC VCC OUTPUT R...

Страница 5: ...2V VIN VCC 0 2V or VIN 0 2V VCC 1 5V 1 7 μA tCDR 7 Chip Deselect to Data Retention Time 0 ns tR 8 Operation Recovery Time tRC ns Data Retention Waveform Notes 7 Tested initially and after any design or process changes that may affect these parameters 8 Full device operation requires linear VCC ramp from VDR to VCC min 100 μs or stable at VCC min 100 μs VCC min VCC min tCDR VDR 1 5V DATA RETENTION ...

Страница 6: ... BHE LOW to Write End 35 ns tSD Data Setup to Write End 25 ns tHD Data Hold from Write End 0 ns tHZWE WE LOW to High Z 10 11 18 ns tLZWE WE HIGH to Low Z 10 10 ns Notes 9 Test conditions for all parameters other than tri state parameters assume signal transition time of 3 ns or less timing reference levels of 1 5V input pulse levels of 0 to 3V and output loading of the specified IOL IOH as shown i...

Страница 7: ...D DATA VALID RC tAA tOHA tRC ADDRESS DATA OUT 50 50 DATA VALID tRC tACE tLZBE tLZCE tPU HIGHIMPEDANCE ICC tHZOE tHZCE tPD tHZBE tLZOE tDBE tDOE IMPEDANCE HIGH ISB DATA OUT OE CE VCC SUPPLY CURRENT BHE BLE ADDRESS Notes 13 The device is continuously selected OE CE VIL BHE BLE or both VIL 14 WE is HIGH for read cycle 15 Address valid before or similar to CE BHE BLE transition LOW Feedback Feedback ...

Страница 8: ...HA tAW tWC tHZOE DATAIN NOTE 18 tBW tSCE DATA IO ADDRESS CE WE OE BHE BLE tHD tSD tPWE tHA tAW tSCE tWC tHZOE DATAIN tBW tSA CE ADDRESS WE DATA IO OE BHE BLE NOTE 18 Notes 16 Data IO is high impedance if OE VIH 17 If CE goes HIGH simultaneously with WE VIH the output remains in a high impedance state 18 During this period the IOs are in output state Do not apply input signals Feedback Feedback ...

Страница 9: ...OW 17 Figure 7 Write Cycle 4 BHE BLE Controlled OE LOW 17 Switching Waveforms continued DATAIN tHD tSD tLZWE tPWE tSA tHA tAW tSCE tWC tHZWE tBW NOTE 18 CE ADDRESS WE DATA IO BHE BLE tHD tSD tSA tHA tAW tWC DATAIN tBW tSCE tPWE tHZWE tLZWE NOTE 18 DATA IO ADDRESS CE WE BHE BLE Feedback Feedback ...

Страница 10: ...15 IO0 IO7 in High Z Read Active ICC L H H L L High Z Output Disabled Active ICC L H H H L High Z Output Disabled Active ICC L H H L H High Z Output Disabled Active ICC L L X L L Data In IO0 IO15 Write Active ICC L L X H L Data In IO0 IO7 IO8 IO15 in High Z Write Active ICC L L X L H Data In IO8 IO15 IO0 IO7 in High Z Write Active ICC Ordering Information Speed ns Ordering Code Package Diagram Pac...

Страница 11: ...CY62146ESL MoBL Document 001 43142 Rev Page 11 of 12 Package Diagrams Figure 8 44 Pin TSOP II 51 85087 51 85087 A Feedback Feedback ...

Страница 12: ...ensee a personal non exclusive non transferable license to copy use modify create derivative works of and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement Any reproduction modification translati...

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