Cypress Semiconductor CY8CKIT-015, Руководство пользователя

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18 CY8CKIT-015 PSoC 1 Power Supervision Kit Guide, Doc. # 001-81218 Rev. **
Example Project
When the inputs to the comparator become nearly equal, the comparator's output may contain
glitches leading to unstable fault detection output. To fairly detect the fault, you must ignore the rare
glitches (transitions from 0 to 1 and 1 to 0) in the comparator's output. To do this, glitch filters are
implemented at the output of the comparators. The glitch filter will indicate a fault only when the com-
parator indicates a fault for a sufficient amount of time. The time required to get an accurate PGOOD
signal is determined by trial and error. This time depends on the glitch filter's clock; for this reason, it
is programmable. In the current implementation, the glitch filter waits for four updates of the compar-
ator output. If all four updates indicate a fault, the glitch filter asserts fault. This way, you can elimi-
nate any glitches from the comparator whose time period is less than four updates.
The PGOOD signal indicates whether the voltage is within the UV/OV range. This is a NOR'ed signal
of the OV and UV comparator outputs. If any fault exists, PGOOD becomes 0 to indicate the fault.
This is routed to a GPIO, and its falling edge interrupt is enabled. Whenever a fault occurs, the CPU
will be interrupted. After the PGOOD interrupt occurs, the OV fault indicator (which is routed to
another GPIO) is checked to find out whether the fault was UV or OV. Within the ISR, all rails are
monitored and checked for their PGOOD status to capture all faulty rails.
Note that on the EBK, the four secondary regulator output voltages are scaled down to normalized
value and routed out as signals C[4:1]. These are provided especially for rapid fault detection to
have an independent multiplexing loop apart from the voltage measurement loop. This provides the
best possible fault detection time. In this example project, those signals are not used because of the
I/O limitation on Port A of the DVK. The signals V[4:1] are used for both fault detection and voltage
monitoring. However,
AN78646 - Integrated Power Manager Using PSoC 1 , implements rapid fault
detection by using C[4:1] signals through a custom cable. Detailed user module (UM) and register-
level implementation of comparators, glitch filters, and other finer details regarding the window com-
parator are discussed in the Appendix section of the application note.
The fault detection feature works based on the following parameters:
■
UV threshold percentage: This indicates the under-voltage threshold for the power rails in terms
of –ve percentage of deviation from nominal voltage.
■
OV threshold percentage: This indicates the over voltage threshold for the power rails in terms of
+ve percentage of deviation from nominal voltage.
Example:
If UV threshold = 5%, then the UV threshold voltage = Nominal voltage × 95%.
If OV threshold = 5%, then the OV threshold voltage = Nominal voltage × 105%.
These voltages are generated by the DAC. The window comparator detects the fault when the input
voltage crosses these two threshold voltages.
These UV/OV percentages can be changed for each rail by changing the definitions in the project’s
configuration.h
file. The default values are 6%, as shown here.