Cypress Semiconductor CY8CKIT-015, Руководство пользователя

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14 CY8CKIT-015 PSoC 1 Power Supervision Kit Guide, Doc. # 001-81218 Rev. **
Example Project
Note also that the PSoC 1 is programmed to shut down all rails on any fault condition. Therefore, all
four green LEDs on the EBK should turn off when jumper J6 is removed. To power the sequencer
again, replace J6 and press and hold the retry switch (SW1 on the CY8CKIT-001 PSoC DVK).
Note
Apart from the signals intended for the expansion board kit, other internal analog and digital
signals from PSoC 1 are also routed to the GPIOs. Because of this, touching the port pins on the
development kit may cause undesirable change in the functionality of the project. If this happens,
reset the PSoC 1 device to restart by pressing the SW4 Reset switch on the CY8CKIT-001 PSoC
DVK.
3.3 PSoC 1 Power Supervisor Solution
The CY8CKIT-035 PSoC Power Supervision Expansion Board Kit (EBK) contains four DC voltage
regulator circuits. They all have enable inputs to allow PSoC 1 to control the power-up and power-
down sequencing of the regulators. They also have the necessary passive components to enable
PSoC 1 to measure their output voltage and load currents using its in-built analog-to-digital converter
(ADC). The regulators have a feedback option that allows PSoC 1 to trim (margin) their output volt-
age.
The EBK has the necessary passive components to enable PSoC 1 to detect under-voltage (UV)
and over-voltage (OV) fault conditions using its internal window comparator hardware.
The CY8CKIT-035 EBK also provides an I2C/SMBus/PMBus compatible header to support systems
that need to communicate with a host controller.
All of this functionality is implemented on a single PSoC. The EBK routes all the input/output signals
for power supervision to a PSoC 1 (CY8C28xxx processor module) mounted on a development kit
platform such as the CY8CKIT-001 PSoC Development Kit. PSoC 1 is not mounted on the EBK
itself.
Figure 3-7 shows a high-level overview of the 4+1 power supervision solution, which can be imple-
mented using the EBK. Up to four secondary regulators can be sequenced through the logic-level
enable outputs (labeled as EN[4]). The four secondary voltage rails along with one primary input
power rail (labeled as V[4+1]) are multiplexed into a 10-bit, SAR ADC configured for a single-ended
input range of 0 mV to 4160 mV at 150 ksps with a 1.5% accurate internal reference. For load cur-
rent measurements of 3.3-V, 2.5-V, and 1.8-V rails across a series shunt resistor (labeled as I[4+1]),
a 14-bit delta-sigma ADC is used along with an instrumentation amplifier with an input range of 0 mV
to 520 mV at 7.8 ksps. For load current measurements of supply rail and 5.0-V rail, a Current Sense
Amplifier (CSA) is used in the EBK. Another 14-bit delta-sigma ADC along with a PGA is used for the
current measurements of these two rails.
The measured voltages are used to increase or decrease the duty cycles of the pulse-width-modula-
tor (PWM) outputs for regulator trimming and margining. The trim or margin PWM outputs from
PSoC 1 (labeled as TR[4]) are filtered with a single RC filter stage on the EBK and fed into the volt-
age feedback input of the regulators. A single time-multiplexed window comparator is implemented
in PSoC 1 using two voltage digital-to-analog converters (DAC) (to set the UV and OV limits for each
rail), two comparators, and two programmable glitch filters. This window comparator loops through
each channel that it monitors (labeled as V[4+1]).