Cypress Semiconductor CY7C1541V18 Скачать руководство пользователя страница 7

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CY7C1541V18, CY7C1556V18
CY7C1543V18, CY7C1545V18

Document Number: 001-05389 Rev. *F

Page 7 of 28

Input

Output Impedance Matching Input

. This input is used to tune the device outputs to the system data bus

impedance. CQ, CQ and Q

[x:0]

output impedance are set to 0.2 x RQ, where RQ is a resistor connected

between ZQ and ground. Alternately, this pin can be connected directly to V

DDQ

, which enables the

minimum impedance mode. This pin cannot be connected directly to GND or left unconnected.

DOFF

Input

DLL Turn Off

−

Active LOW

. Connecting this pin to ground turns off the DLL inside the device.The timings

in the DLL turned off operation are different from those listed in this data sheet. For normal operation, this
pin can be connected to a pull up through a 10 K

or less pull up resistor. The device behaves in QDR-I

mode when the DLL is turned off. In this mode, the device can be operated at a frequency of up to 167
MHz with QDR-I timing.

TDO

Output

TDO for JTAG

TCK

Input

TCK Pin for JTAG

TDI

Input

TDI Pin for JTAG

TMS

Input

TMS Pin for JTAG

N/A

Not Connected to the Die

. Can be tied to any voltage level.

NC/144M

N/A

Not Connected to the Die

. Can be tied to any voltage level.

NC/288M

N/A

Not Connected to the Die.

Can be tied to any voltage level.

REF

Input-

Reference

Reference Voltage Input

. Static input used to set the reference level for HSTL inputs and Outputs as

well as AC measurement points.

Power Supply

Power Supply Inputs to the Core of the Device

Ground

Ground for the Device

DDQ

Power Supply

Power Supply Inputs for the Outputs of the Device

Pin Definitions

(continued)

Pin Name

Pin Description

[+] Feedback

Содержание CY7C1541V18

Страница 1: ...f two separate ports the read port and the write port to access the memory array The read port has dedicated data outputs to support read operations and the write port has dedicated data inputs to sup...

Страница 2: ...g Reg 16 21 32 8 NWS 1 0 VREF Write Add Decode Write Reg 16 A 20 0 21 2M x 8 Array 2M x 8 Array 2M x 8 Array 8 CQ CQ DOFF Q 7 0 8 QVLD 8 8 8 Write Reg Write Reg Write Reg 2M x 9 Array CLK A 20 0 Gen K...

Страница 3: ...8 BWS 1 0 VREF Write Add Decode Write Reg 36 A 19 0 20 1M x 18 Array 1M x 18 Array 1M x 18 Array 18 CQ CQ DOFF Q 17 0 18 QVLD 18 18 18 Write Reg Write Reg Write Reg 512K x 36 Array CLK A 18 0 Gen K K...

Страница 4: ...S VSS VSS VDDQ NC NC Q0 M NC NC NC VSS VSS VSS VSS VSS NC NC D0 N NC D7 NC VSS A A A VSS NC NC NC P NC NC Q7 A A QVLD A A NC NC NC R TDO TCK A A A NC A A A TMS TDI CY7C1556V18 8M x 9 1 2 3 4 5 6 7 8 9...

Страница 5: ...C D0 Q0 R TDO TCK A A A NC A A A TMS TDI CY7C1545V18 4M x 36 1 2 3 4 5 6 7 8 9 10 11 A CQ NC 288M A WPS BWS2 K BWS1 RPS A NC 144M CQ B Q27 Q18 D18 A BWS3 K BWS0 A D17 Q17 Q8 C D27 Q28 D19 VSS A NC A V...

Страница 6: ...is organized as 8M x 8 4 arrays each of 2M x 8 for CY7C1541V18 8M x 9 4 arrays each of 2M x 9 for CY7C1556V18 4M x 18 4 arrays each of 1M x 18 for CY7C1543V18 and 2M x 36 4 arrays each of 512K x 36 f...

Страница 7: ...be connected to a pull up through a 10 K or less pull up resistor The device behaves in QDR I mode when the DLL is turned off In this mode the device can be operated at a frequency of up to 167 MHz wi...

Страница 8: ...he next rising edge of the positive input clock K This enables for a seamless transition between devices without the insertion of wait states in a depth expanded memory Write Operations Write operatio...

Страница 9: ...e input clock of the QDR II The timing for the echo clocks is shown in Switching Characteristics on page 23 Valid Data Indicator QVLD QVLD is provided on the QDR II to simplify data capture on high sp...

Страница 10: ...portion of a write sequence CY7C1541V18 only the upper nibble D 7 4 is written into the device D 3 0 remains unaltered CY7C1543V18 only the upper byte D 17 9 is written into the device D 8 0 remains...

Страница 11: ...e device D 35 9 remains unaltered L H H H L H During the Data portion of a write sequence only the lower byte D 8 0 is written into the device D 35 9 remains unaltered H L H H L H During the Data port...

Страница 12: ...be serially loaded into the instruction register This register is loaded when it is placed between the TDI and TDO pins as shown in TAP Controller Block Diagram on page 15 Upon power up the instructio...

Страница 13: ...t the data by putting the TAP into the Shift DR state This places the boundary scan register between the TDI and TDO pins PRELOAD places an initial data pattern at the latched parallel outputs of the...

Страница 14: ...State Diagram TEST LOGIC RESET TEST LOGIC IDLE SELECT DR SCAN CAPTURE DR SHIFT DR EXIT1 DR PAUSE DR EXIT2 DR UPDATE DR 1 0 1 1 0 1 0 1 0 0 0 1 1 1 0 1 0 1 0 0 0 1 0 1 1 0 1 0 0 1 1 0 SELECT IR SCAN CA...

Страница 15: ...Voltage 0 65VDD VDD 0 3 V VIL Input LOW Voltage 0 3 0 35VDD V IX Input and Output Load Current GND VI VDD 5 5 A 0 0 1 2 29 30 31 Boundary Scan Register Identification Register 0 1 2 108 0 1 2 Instruct...

Страница 16: ...TDI Hold after Clock Rise 5 ns tCH Capture Hold after Clock Rise 5 ns Output Times tTDOV TCK Clock LOW to TDO Valid 10 ns tTDOX TCK Clock LOW to TDO Invalid 0 ns TAP Timing and Test Conditions Figure...

Страница 17: ...on Codes Instruction Code Description EXTEST 000 Captures the input and output ring contents IDCODE 001 Loads the ID register with the vendor ID code and places the register between TDI and TDO This o...

Страница 18: ...35 10E 63 2A 91 3L 8 9R 36 10D 64 1A 92 1M 9 11P 37 9E 65 2B 93 1L 10 10P 38 10C 66 3B 94 3N 11 10N 39 11D 67 1C 95 3M 12 9P 40 9C 68 1B 96 1N 13 10M 41 9D 69 3D 97 2M 14 11N 42 11B 70 3C 98 3P 15 9M...

Страница 19: ...ovide stable power and clock K K for 2048 cycles to lock the DLL DLL Constraints DLL uses K clock as its synchronizing input The input must have low phase jitter which is specified as tKC Var The DLL...

Страница 20: ...GH Voltage Note 19 VDDQ 2 0 12 VDDQ 2 0 12 V VOL Output LOW Voltage Note 20 VDDQ 2 0 12 VDDQ 2 0 12 V VOH LOW Output HIGH Voltage IOH 0 1 mA Nominal Impedance VDDQ 0 2 VDDQ V VOL LOW Output LOW Voltag...

Страница 21: ...e 14 Parameter Description Test Conditions Min Typ Max Unit VIH Input HIGH Voltage VREF 0 2 VDDQ 0 24 V VIL Input LOW Voltage 0 24 VREF 0 2 V Capacitance Tested initially and after any design or proce...

Страница 22: ...1 11 82 C W JC Thermal Resistance Junction to Case 2 33 C W Figure 4 AC Test Loads and Waveforms 1 25V 0 25V R 50 5 pF INCLUDING JIG AND SCOPE ALL INPUT PULSES Device RL 50 Z0 50 VREF 0 75V VREF 0 75V...

Страница 23: ...ns tCQDOH tCQHQX Echo Clock High to Data Invalid 0 2 0 2 0 2 ns tCQH tCQHCQL Output Clock CQ CQ HIGH 26 0 88 1 03 1 15 ns tCQHCQH tCQHCQH CQ Clock Rise to CQ Clock Rise 26 rising edge to rising edge 0...

Страница 24: ...PS K K DON T CARE UNDEFINED CQ CQ tCQOH CCQO t tCQOH CCQO t tQVLD QVLD tQVLD Read Latency 2 0 Cycles CLZ t t CO tDOH tCQDOH CQD t tCHZ Q00 Q01 Q20 Q02 Q21 Q03 Q22 Q23 tCQH tCQHCQH Q Notes 31 Q00 refer...

Страница 25: ...all Fine Pitch Ball Grid Array 15 x 17 x 1 4 mm Industrial CY7C1556V18 375BZI CY7C1543V18 375BZI CY7C1545V18 375BZI CY7C1541V18 375BZXI 51 85195 165 Ball Fine Pitch Ball Grid Array 15 x 17 x 1 4 mm Pb...

Страница 26: ...00BZXC CY7C1541V18 300BZI 51 85195 165 Ball Fine Pitch Ball Grid Array 15 x 17 x 1 4 mm Industrial CY7C1556V18 300BZI CY7C1543V18 300BZI CY7C1545V18 300BZI CY7C1541V18 300BZXI 51 85195 165 Ball Fine P...

Страница 27: ...CY7C1545V18 Document Number 001 05389 Rev F Page 27 of 28 Package Diagram Figure 6 165 ball FBGA 15 x 17 x 1 4 mm 51 85195 0 2 2 8 8 8 3 4 0 0 2 2 4 0 6 7 44 6 7 0 2 0 2 3 2 0 490 3 2 3 3 4 3 0 7 4 G...

Страница 28: ...ice to the materials described herein Cypress does not assume any liability arising out of the application or use of any product or circuit described herein Cypress does not authorize its products for...

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