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CY7C1460AV33
CY7C1462AV33
CY7C1464AV33

Document #: 38-05353 Rev. *D

Page 23 of 27

250

CY7C1460AV33-250AXC

51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free

Commercial

CY7C1462AV33-250AXC

CY7C1460AV33-250BZC

51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm)

CY7C1462AV33-250BZC

CY7C1460AV33-250BZXC 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Lead-Free

CY7C1462AV33-250BZXC

CY7C1464AV33-250BGC

51-85167 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm)

CY7C1464AV33-250BGXC

209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) Lead-Free

CY7C1460AV33-250AXI

51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free

Industrial

CY7C1462AV33-250AXI

CY7C1460AV33-250BZI

51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm)

CY7C1462AV33-250BZI

CY7C1460AV33-250BZXI

51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Lead-Free

CY7C1462AV33-250BZXI

CY7C1464AV33-250BGI

51-85167 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm)

CY7C1464AV33-250BGXI

209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) Lead-Free

Ordering Information

(continued)

Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or

visit

www.cypress.com

for actual products offered.

Speed

(MHz)

Ordering Code

Package

Diagram

Part and Package Type

Operating

Range

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Содержание CY7C1460AV33

Страница 1: ...required to enable consecutive Read Write operations with data being trans ferred on every clock cycle This feature dramatically improves the throughput of data in systems that require frequent Write...

Страница 2: ...am CY7C1462AV33 2M x 18 A0 A1 A C MODE CE1 CE2 CE3 OE READ LOGIC DQs DQPa DQPb DQPc DQPd DQPe DQPf DQPg DQPh D A T A S T E E R I N G O U T P U T B U F F E R S MEMORY ARRAY E E INPUT REGISTER0 ADDRESS...

Страница 3: ...1460AV33 100 pin TQFP Pinout A A A A A 1 A 0 V SS V DD A A A A A A A NC NC VDDQ VSS NC DQPa DQa DQa VSS VDDQ DQa DQa VSS NC VDD DQa DQa VDDQ VSS DQa DQa NC NC VSS VDDQ NC NC NC NC NC NC VDDQ VSS NC NC...

Страница 4: ...VDD NC VDD DQa VDD VDDQ DQa VDDQ VDD VDD VDDQ VDD VDDQ DQa VDDQ A A VSS A A A DQb DQb DQb ZZ DQa DQa DQPa DQa A VDDQ A 2 3 4 5 6 7 1 A B C D E F G H J K L M N P R TDO NC 576M NC 1G NC NC DQPb NC DQb...

Страница 5: ...er is advanced When LOW a new address can be loaded into the device for an access After being deselected ADV LD should be driven LOW in order to load a new address Pin Configurations continued A B C D...

Страница 6: ...g the data portion of a write sequence during the first clock when emerging from a deselected state and when the device is deselected regardless of the state of OE DQPa DQPb DQPc DQPd DQPe DQPf DQPg D...

Страница 7: ...h burst counters use A0 and A1 in the burst sequence and will wrap around when incre mented sufficiently A HIGH input on ADV LD will increment the internal burst counter regardless of the state of chi...

Страница 8: ...ZZS Device operation to ZZ ZZ VDD 0 2V 2tCYC ns tZZREC ZZ recovery time ZZ 0 2V 2tCYC ns tZZI ZZ active to sleep current This parameter is sampled 2tCYC ns tRZZI ZZ Inactive to exit sleep current This...

Страница 9: ...e Byte b DQb and DQPb L H H L H Write Bytes b a L H H L L Write Byte c DQc and DQPc L H L H H Write Bytes c a L H L H L Write Bytes c b L H LL L H Write Bytes c b a L H L L L Write Byte d DQd and DQPd...

Страница 10: ...e unconnected if the TAP is unused in an application TDI is connected to the most signif icant bit MSB of any register See Tap Controller Block Diagram Test Data Out TDO The TDO output ball is used to...

Страница 11: ...p or whenever the TAP controller is given a test logic reset state SAMPLE Z The SAMPLE Z instruction causes the boundary scan register to be connected between the TDI and TDO pins when the TAP control...

Страница 12: ...e TAP controller is in the Test Logic Reset state Reserved These instructions are not implemented but are reserved for future use Do not use these instructions TAP Timing TAP AC Switching Characterist...

Страница 13: ...V VDDQ 2 5V 2 1 V VOL1 Output LOW Voltage IOL 8 0 mA VDDQ 3 3V 0 4 V IOL 1 0 mA VDDQ 2 5V 0 4 V VOL2 Output LOW Voltage IOL 100 A VDDQ 3 3V 0 2 V VDDQ 2 5V 0 2 V VIH Input HIGH Voltage VDDQ 3 3V 2 0...

Страница 14: ...the vendor ID code and places the register between TDI and TDO This operation does not affect SRAM operations SAMPLE Z 010 Captures I O ring contents Places the boundary scan register between TDI and...

Страница 15: ...5 P8 30 E10 55 B1 80 R2 6 R8 31 D10 56 A1 81 P3 7 R9 32 C11 57 C1 82 R3 8 P9 33 A11 58 D1 83 P2 9 P10 34 B11 59 E1 84 R4 10 R10 35 A10 60 F1 85 P4 11 R11 36 B10 61 G1 86 N5 12 H11 37 A9 62 D2 87 P6 13...

Страница 16: ...12 U9 47 10F 82 4B 117 1P 13 P6 48 10E 83 3C 118 2R 14 W11 49 11E 84 3B 119 1R 15 W10 50 11D 85 3A 120 2T 16 V11 51 10D 86 2A 121 1T 17 V10 52 11C 87 1A 122 2U 18 U11 53 10C 88 2B 123 1U 19 U10 54 11...

Страница 17: ...or 2 5V I O IOL 1 0 mA 0 4 V VIH Input HIGH Voltage 15 for 3 3V I O 2 0 VDD 0 3V V for 2 5V I O 1 7 VDD 0 3V V VIL Input LOW Voltage 15 for 3 3V I O 0 3 0 8 V for 2 5V I O 0 3 0 7 V IX Input Leakage C...

Страница 18: ...scription Test Conditions 100 TQFP Package 165 FBGA Package 209 FBGA Package Unit JA Thermal Resistance Junction to Ambient Test conditions follow standard test methods and procedures for measuring th...

Страница 19: ...ip Select Set up 1 2 1 4 1 5 ns Hold Times tAH Address Hold After CLK Rise 0 3 0 4 0 5 ns tDH Data Input Hold After CLK Rise 0 3 0 4 0 5 ns tCENH CEN Hold After CLK Rise 0 3 0 4 0 5 ns tWEH WE BWx Hol...

Страница 20: ...the Burst sequence is determined by the status of the MODE 0 Linear 1 Interleaved Burst operations are optional WRITE D A1 1 2 3 4 5 6 7 8 9 CLK t CYC tCL tCH 10 CE tCEH tCES WE CEN tCENH tCENS BWx AD...

Страница 21: ...ditions to deselect the device 29 I Os are in High Z when exiting ZZ sleep mode NOP STALL and DESELECT Cycles 24 25 27 ZZ Mode Timing 28 29 Switching Waveforms continued READ Q A3 4 5 6 7 8 9 10 CLK C...

Страница 22: ...0AV33 167BZXI 51 85165 165 ball Fine Pitch Ball Grid Array 15 x 17 x 1 4 mm Lead Free CY7C1462AV33 167BZXI CY7C1464AV33 167BGI 51 85167 209 ball Fine Pitch Ball Grid Array 14 22 1 76 mm CY7C1464AV33 1...

Страница 23: ...Y7C1460AV33 250AXI 51 85050 100 Pin Thin Quad Flat Pack 14 x 20 x 1 4 mm Lead Free Industrial CY7C1462AV33 250AXI CY7C1460AV33 250BZI 51 85165 165 ball Fine Pitch Ball Grid Array 15 x 17 x 1 4 mm CY7C...

Страница 24: ...SIDE 3 DIMENSIONS IN MILLIMETERS BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH 0 30 0 08 0 65 20 00 0 10 22 00 0 20 1 40 0 05 12 1 1 60 MAX 0 05 MIN 0 60 0 15 0 MIN 0 25 0...

Страница 25: ...00 1 00 0 45 0 05 165X 0 25 M C A B 0 05 M C B A 0 15 4X 0 35 1 40 MAX SEATING PLANE 0 53 0 05 0 25 C 0 15 C PIN 1 CORNER TOP VIEW BOTTOM VIEW 2 3 4 5 6 7 8 9 10 10 00 14 00 B C D E F G H J K L M N 11...

Страница 26: ...n express written agreement with Cypress Furthermore Cypress does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be exp...

Страница 27: ...o 1 5 ns for 200 MHz Speed Bin Added lead free information for 100 pin TQFP and 165 FBGA and 209 BGA packages B 331778 See ECN SYT Modified Address Expansion balls in the pinouts for 165 FBGA and 209...

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