background image

CY7C1410AV18, CY7C1425AV18
CY7C1412AV18, CY7C1414AV18

Document #: 38-05615 Rev. *E

Page 13 of 29

IDCODE

The IDCODE instruction loads a vendor-specific, 32-bit code into
the instruction register. It also places the instruction register
between the TDI and TDO pins and shifts the IDCODE out of the
device when the TAP controller enters the Shift-DR state. The
IDCODE instruction is loaded into the instruction register at
power up or whenever the TAP controller is supplied a
Test-Logic-Reset state.

SAMPLE Z

The SAMPLE Z instruction connects the boundary scan register
between the TDI and TDO pins when the TAP controller is in a
Shift-DR state. The SAMPLE Z command puts the output bus
into a High-Z state until the next command is supplied during the
Update IR state.

SAMPLE/PRELOAD

SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When
the SAMPLE/PRELOAD instructions are loaded into the
instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the input and output pins is captured
in the boundary scan register.

The user must be aware that the TAP controller clock can only
operate at a frequency up to 20 MHz, while the SRAM clock
operates more than an order of magnitude faster. Because there
is a large difference in the clock frequencies, it is possible that
during the Capture-DR state, an input or output undergoes a
transition. The TAP may then try to capture a signal while in
transition (metastable state). This does not harm the device, but
there is no guarantee as to the value that is captured.
Repeatable results may not be possible.

To guarantee that the boundary scan register captures the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller's capture setup plus hold
times (t

CS

 and t

CH

). The SRAM clock input might not be captured

correctly if there is no way in a design to stop (or slow) the clock
during a SAMPLE/PRELOAD instruction. If this is an issue, it is
still possible to capture all other signals and simply ignore the
value of the CK and CK captured in the boundary scan register.

After the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the boundary
scan register between the TDI and TDO pins.

PRELOAD places an initial data pattern at the latched parallel
outputs of the boundary scan register cells before the selection
of another boundary scan test operation.

The shifting of data for the SAMPLE and PRELOAD phases can
occur concurrently when required, that is, while the data
captured is shifted out, the preloaded data can be shifted in.

BYPASS

When the BYPASS instruction is loaded in the instruction register
and the TAP is placed in a Shift-DR state, the bypass register is
placed between the TDI and TDO pins. The advantage of the
BYPASS instruction is that it shortens the boundary scan path
when multiple devices are connected together on a board.

EXTEST

The EXTEST instruction drives the preloaded data out through
the system output pins. This instruction also connects the
boundary scan register for serial access between the TDI and
TDO in the Shift-DR controller state.

EXTEST OUTPUT BUS TRI-STATE

IEEE Standard 1149.1 mandates that the TAP controller be able
to put the output bus into a tri-state mode.

The boundary scan register has a special bit located at bit #108.
When this scan cell, called the “extest output bus tri-state,” is
latched into the preload register during the Update-DR state in
the TAP controller, it directly controls the state of the output
(Q-bus) pins, when the EXTEST is entered as the current
instruction. When HIGH, it enables the output buffers to drive the
output bus. When LOW, this bit places the output bus into a
High-Z condition.

This bit can be set by entering the SAMPLE/PRELOAD or
EXTEST command, and then shifting the desired bit into that cell,
during the Shift-DR state. During Update-DR, the value loaded
into that shift-register cell latches into the preload register. When
the EXTEST instruction is entered, this bit directly controls the
output Q-bus pins. Note that this bit is pre-set LOW to enable the
output when the device is powered up, and also when the TAP
controller is in the Test-Logic-Reset state.

Reserved

These instructions are not implemented but are reserved for
future use. Do not use these instructions.

[+] Feedback 

Содержание CY7C1410AV18

Страница 1: ...two separate ports the read port and the write port to access the memory array The read port has data outputs to support read operations and the write port has data inputs to support write operations...

Страница 2: ...d Data Reg RPS WPS Control Logic Address Register Reg Reg Reg 8 21 16 8 NWS 1 0 VREF Write Add Decode Write Reg 8 A 20 0 21 CQ CQ DOFF Q 7 0 8 8 Write Reg C C 2M x 8 Array 8 2M x 9 Array CLK A 20 0 Ge...

Страница 3: ...RPS WPS Control Logic Address Register Reg Reg Reg 18 20 36 18 BWS 1 0 VREF Write Add Decode Write Reg 18 A 19 0 20 CQ CQ DOFF Q 17 0 18 18 Write Reg C C 1M x 18 Array 18 512K x 36 Array CLK A 18 0 Ge...

Страница 4: ...DQ VSS VSS VSS VDDQ NC NC Q0 M NC NC NC VSS VSS VSS VSS VSS NC NC D0 N NC D7 NC VSS A A A VSS NC NC NC P NC NC Q7 A A C A A NC NC NC R TDO TCK A A A C A A A TMS TDI CY7C1425AV18 4M x 9 1 2 3 4 5 6 7 8...

Страница 5: ...NC D0 Q0 R TDO TCK A A A C A A A TMS TDI CY7C1414AV18 1M x 36 1 2 3 4 5 6 7 8 9 10 11 A CQ NC 288M NC 72M WPS BWS2 K BWS1 RPS A NC 144M CQ B Q27 Q18 D18 A BWS3 K BWS0 A D17 Q17 Q8 C D27 Q28 D19 VSS A...

Страница 6: ...for CY7C1410AV18 4M x 9 2 arrays each of 2M x 9 for CY7C1425AV18 2M x 18 2 arrays each of 1M x 18 for CY7C1412AV18 and 1M x 36 2 arrays each of 512K x 36 for CY7C1414AV18 Therefore only 21 address in...

Страница 7: ...Alternatively this pin can be connected directly to VDDQ which enables the minimum impedance mode This pin cannot be connected directly to GND or left unconnected DOFF Input DLL Turn Off Active LOW Co...

Страница 8: ...between devices without the insertion of wait states in a depth expanded memory Write Operations Write operations are initiated by asserting WPS active at the rising edge of the positive input clock K...

Страница 9: ...to K and CQ is generated with respect to K The timing for the echo clocks is shown in the Switching Characteristics on page 23 DLL These chips use a Delay Lock Loop DLL that is designed to function b...

Страница 10: ...0 is written into the device D 17 9 remains unaltered H L L H During the data portion of a write sequence CY7C1410AV18 only the upper nibble D 7 4 is written into the device D 3 0 remains unaltered CY...

Страница 11: ...into the device D 35 9 remains unaltered L H H H L H During the Data portion of a write sequence only the lower byte D 8 0 is written into the device D 35 9 remains unaltered H L H H L H During the Da...

Страница 12: ...edge of TCK Instruction Register Three bit instructions can be serially loaded into the instruction register This register is loaded when it is placed between the TDI and TDO pins as shown in TAP Con...

Страница 13: ...scan register After the data is captured it is possible to shift out the data by putting the TAP into the Shift DR state This places the boundary scan register between the TDI and TDO pins PRELOAD pla...

Страница 14: ...oller follows 9 TEST LOGIC RESET TEST LOGIC IDLE SELECT DR SCAN CAPTURE DR SHIFT DR EXIT1 DR PAUSE DR EXIT2 DR UPDATE DR 1 0 1 1 0 1 0 1 0 0 0 1 1 1 0 1 0 1 0 0 0 1 0 1 1 0 1 0 0 1 1 0 SELECT IR SCAN...

Страница 15: ...GH Voltage 0 65VDD VDD 0 3 V VIL Input LOW Voltage 0 3 0 35VDD V IX Input and Output Load Current GND VI VDD 5 5 A 0 0 1 2 29 30 31 Boundary Scan Register Identification Register 0 1 2 108 0 1 2 Instr...

Страница 16: ...IH TDI Hold after Clock Rise 5 ns tCH Capture Hold after Clock Rise 5 ns Output Times tTDOV TCK Clock LOW to TDO Valid 10 ns tTDOX TCK Clock LOW to TDO Invalid 0 ns TAP Timing and Test Conditions Figu...

Страница 17: ...ruction Codes Instruction Code Description EXTEST 000 Captures the input and output ring contents IDCODE 001 Loads the ID register with the vendor ID code and places the register between TDI and TDO T...

Страница 18: ...8P 35 10E 63 2A 91 3L 8 9R 36 10D 64 1A 92 1M 9 11P 37 9E 65 2B 93 1L 10 10P 38 10C 66 3B 94 3N 11 10N 39 11D 67 1C 95 3M 12 9P 40 9C 68 1B 96 1N 13 10M 41 9D 69 3D 97 2M 14 11N 42 11B 70 3C 98 3P 15...

Страница 19: ...K K for 1024 cycles to lock the DLL DLL Constraints DLL uses K clock as its synchronizing input The input must have low phase jitter which is specified as tKC Var The DLL functions at frequencies dow...

Страница 20: ...HIGH Voltage Note 16 VDDQ 2 0 12 VDDQ 2 0 12 V VOL Output LOW Voltage Note 17 VDDQ 2 0 12 VDDQ 2 0 12 V VOH LOW Output HIGH Voltage IOH 0 1 mA Nominal Impedance VDDQ 0 2 VDDQ V VOL LOW Output LOW Vol...

Страница 21: ...20 x36 475 200MHz x8 350 mA x9 350 x18 370 x36 420 167MHz x8 330 mA x9 330 x18 345 x36 390 AC Electrical Characteristics Over the Operating Range 11 Parameter Description Test Conditions Min Typ Max U...

Страница 22: ...tion to Ambient Test conditions follow standard test methods and procedures for measuring thermal impedance in accordance with EIA JESD51 17 2 C W JC Thermal Resistance Junction to Case 3 2 C W Figure...

Страница 23: ...gle Clock Mode to Data Valid 0 45 0 45 0 50 ns tDOH tCHQX Data Output Hold after Output C C Clock Rise Active to Active 0 45 0 45 0 50 ns tCCQO tCHCQV C C Clock Rise to Echo Clock Valid 0 45 0 45 0 50...

Страница 24: ...D50 D51 D61 D31 D11 D10 D60 Q C C DON T CARE UNDEFINED t CQ CQ tKHCH tCO tKHCH tCLZ CHZ tKH tKL Q00 Q01 Q20 tKHKH tCYC Q21 Q40 Q41 tCQD tDOH tCCQO tCQOH tCCQO tCQOH tCQDOH Notes 26 Q00 refers to outp...

Страница 25: ...Fine Pitch Ball Grid Array 15 x 17 x 1 4 mm Industrial CY7C1425AV18 250BZI CY7C1412AV18 250BZI CY7C1414AV18 250BZI CY7C1410AV18 250BZXI 51 85195 165 Ball Fine Pitch Ball Grid Array 15 x 17 x 1 4 mm Pb...

Страница 26: ...8 167BZXC CY7C1410AV18 167BZI 51 85195 165 Ball Fine Pitch Ball Grid Array 15 x 17 x 1 4 mm Industrial CY7C1425AV18 167BZI CY7C1412AV18 167BZI CY7C1414AV18 167BZI CY7C1410AV18 167BZXI 51 85195 165 Bal...

Страница 27: ...0 25 M C A B 0 05 M C B A 0 15 4X 0 35 0 06 1 40 MAX SEATING PLANE 0 53 0 05 0 25 C 0 15 C PIN 1 CORNER TOP VIEW BOTTOM VIEW 2 3 4 5 6 7 8 9 10 10 00 14 00 B C D E F G H J K L M N 11 11 10 9 8 6 7 5 4...

Страница 28: ...Power up sequence and Wave form on page 19 Added foot notes 13 14 15 on page 19 Replaced Three state with Tri state Changed the description of IX from Input Load Current to Input Leakage Current on pa...

Страница 29: ...presentation of this Source Code except as specified above is prohibited without the express written permission of Cypress Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND EXPRESS OR IMPLIED WITH REGA...

Отзывы: