CY7C138, CY7C139
Document #: 38-06037 Rev. *D
Page 7 of 17
Figure 5. Read Timing with Port-to-Port Delay (M/S = L)
[20, 21]
Figure 6. Write Cycle No. 1: OE Three-States Data I/Os (Either Port)
[22, 23, 24]
Switching Waveforms
(continued)
t
ACE
t
LZOE
t
DOE
t
HZOE
t
HZCE
DATA VALID
DATA OUT
SEM or CE
OE
t
LZCE
t
PU
I
CC
I
SB
t
PD
VALID
t
DDD
t
WDD
MATCH
MATCH
R/W
R
DATA
INR
DATA
OUTL
t
WC
ADDRESS
R
t
PWE
VALID
t
SD
t
HD
ADDRESS
L
Notes
16. R/W is HIGH for read cycle.
17. Device is continuously selected CE = LOW and OE = LOW. This waveform cannot be used for semaphore reads.
18. Address valid prior to or coincident with CE transition LOW.
19. CE
L
= L, SEM = H when accessing RAM. CE = H, SEM = L when accessing semaphores.
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