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CY7C1361C
CY7C1363C

Document #: 38-05541 Rev. *F

Page 23 of 31

Write Cycle Timing

[22, 23]

Note:

23. Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BW

LOW.

Timing Diagrams

(continued)

tCYC

CLK

tADH

tADS

ADDRESS

tAH

tAS

tCEH

tCES

High-Z

BURST READ

BURST WRITE

D(A2)

D(A2 + 1)

D(A1)

D(A3)

D(A3 + 1)

D(A3 + 2)

D(A2 + 3)

Extended BURST WRITE

D(A2 + 2)

Single WRITE

tADH

tADS

tADH

tADS

OEHZ

tADVH

tADVS

tWEH

tWES

WEH

WES

Byte write signals are ignored for first cycle when
ADSP initiates burst

ADSC extends burst

ADV suspends burst

DON’T CARE

UNDEFINED

ADSP

ADSC

BWE,

ADV

Data in (D)

Data Out (Q)

[+] Feedback

Содержание CY7C1361C

Страница 1: ...positive edge triggered Clock Input CLK The synchronous inputs include all addresses all data inputs address pipelining Chip Enable CE1 depth expansion Chip Enables CE2 and CE3 2 Burst Control inputs...

Страница 2: ...EGISTER BYTE WRITE REGISTER DQD DQPD BYTE WRITE REGISTER DQD DQPD BYTE WRITE REGISTER DQC DQPC BYTE WRITE REGISTER DQB DQPB BYTE WRITE REGISTER DQA DQPA BYTE WRITE REGISTER Logic Block Diagram CY7C136...

Страница 3: ...60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 MODE CY7C1361C 256K x 36 VSS DNU A A A A A 1 A 0 NC NC V SS V DD NC A A A A A A A A A NC NC VDDQ VSSQ NC DQPA...

Страница 4: ...61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 MODE CY7C1361C 256K x 36 VSS DNU A A A A A 1 A 0 NC NC V SS V DD A A A A A A A A NC NC VDDQ VSSQ NC DQPA...

Страница 5: ...C NC CE1 OE ADV GW VSS VSS VSS VSS VSS VSS VSS VSS DQPA MODE DQPD DQPB BWB BWC NC VDD NC BWA NC BWE BWD ZZ 2 3 4 5 6 7 1 A B C D E F G H J K L M N P R T U VDDQ NC 288M NC 144M NC DQB DQB DQB DQB A A A...

Страница 6: ...C DQA DQA VDD VDDQ VDD VDDQ DQB VDD NC VDD DQA VDD VDDQ DQA VDDQ VDD VDD VDDQ VDD VDDQ DQA VDDQ A A VSS A A A DQB DQB DQB ZZ DQA DQA DQPA DQA A VDDQ A CY7C1363C 512K x 18 A0 A VSS 2 3 4 5 6 7 1 A B C...

Страница 7: ...from Processor sampled on the rising edge of CLK active LOW When asserted LOW addresses presented to the device are captured in the address registers A 1 0 are also loaded into the burst counter When...

Страница 8: ...VDD through a pull up resistor This pin is not available on TQFP packages TMS JTAG serial input Synchronous Serial data In to the JTAG circuit Sampled on the rising edge of TCK If the JTAG feature is...

Страница 9: ...appropriate data will be latched and written into the device Byte writes are allowed All I Os are tri stated during a byte write Since this is a common I O device the asynchronous OE input signal must...

Страница 10: ...H H L H Tri state Read Cycle Continue Burst Next H X X L X H L H L L H Q Read Cycle Continue Burst Next H X X L X H L H H L H Tri state Write Cycle Continue Burst Next X X X L H H L L X L H D Write Cy...

Страница 11: ...DQPA H L L H H L Write Bytes D B DQPD DQPA H L L H L H Write Bytes D B A DQPD DQPB DQPA H L L H L L Write Bytes D B DQPD DQPB H L L L H H Write Bytes D B A DQPD DQPC DQPA H L L L H L Write Bytes D C...

Страница 12: ...rnally resulting in a logic HIGH level Test Data In TDI The TDI ball is used to serially input information into the registers and can be connected to the input of any of the registers The register bet...

Страница 13: ...hen the instruction register is placed between TDI and TDO During this state instructions are shifted through the instruction register through the TDI and TDO balls To execute the instruction once it...

Страница 14: ...for future use Do not use these instructions TAP Timing TAP AC Switching Characteristics Over the Operating Range 9 10 Parameter Parameter Min Max Unit Clock tTCYC TCK Clock Cycle Time 50 ns tTF TCK C...

Страница 15: ...1 V VOL1 Output LOW Voltage IOL 8 0 mA VDDQ 3 3V 0 4 V IOL 8 0 mA VDDQ 2 5V 0 4 V VOL2 Output LOW Voltage IOL 100 A VDDQ 3 3V 0 2 V VDDQ 2 5V 0 2 V VIH Input HIGH Voltage VDDQ 3 3V 2 0 VDD 0 3 V VDDQ...

Страница 16: ...ode and places the register between TDI and TDO This operation does not affect SRAM operations SAMPLE Z 010 Captures I O ring contents Places the boundary scan register between TDI and TDO Forces all...

Страница 17: ...0 M2 DQB 15 E7 DQB 51 L1 DQD 15 E7 DQA 51 L1 DQB 16 F6 DQB 52 K2 DQD 16 F6 DQA 52 K2 DQB 17 G7 DQB 53 Internal Internal 17 G7 DQA 53 Internal Internal 18 H6 DQB 54 H1 DQC 18 H6 DQA 54 H1 DQB 19 T7 ZZ...

Страница 18: ...50 L1 DQB 15 D11 DQB 51 K1 DQD 15 D11 DQA 51 K1 DQB 16 E11 DQB 52 J1 DQD 16 E11 DQA 52 J1 DQB 17 F11 DQB 53 Internal Internal 17 F11 DQA 53 Internal Internal 18 G11 DQB 54 G2 DQC 18 G11 DQA 54 G2 DQB...

Страница 19: ...I O 1 7 VDD 0 3V V VIL Input LOW Voltage 13 for 3 3V I O 0 3 0 8 V for 2 5V I O 0 3 0 7 V IX Input Leakage Current except ZZ and MODE GND VI VDDQ 5 5 A Input Current of MODE Input VSS 30 A Input VDD...

Страница 20: ...on to Ambient Test conditions follow standard test methods and procedures for measuring thermal impedance per EIA JESD51 29 41 34 1 16 8 C W JC Thermal Resistance Junction to Case 6 31 14 0 3 0 C W AC...

Страница 21: ...0 5 ns tADH ADSP ADSC Hold After CLK Rise 0 5 0 5 ns tWEH GW BWE BW A D Hold After CLK Rise 0 5 0 5 ns tADVH ADV Hold After CLK Rise 0 5 0 5 ns tDH Data Input Hold After CLK Rise 0 5 0 5 ns tCEH Chip...

Страница 22: ...GH or CE2 is LOW or CE3 is HIGH tCYC tCL CLK tADH tADS ADDRESS t CH tAH tAS A1 tCEH tCES Data Out Q High Z tCLZ tDOH tCDV tOEHZ tCDV Single READ BURST READ tOEV tOELZ tCHZ Burst wraps around to its in...

Страница 23: ...ADDRESS t CH tAH tAS A1 tCEH tCES High Z BURST READ BURST WRITE D A2 D A2 1 D A2 1 D A1 D A3 D A3 1 D A3 2 D A2 3 A2 A3 Extended BURST WRITE D A2 2 Single WRITE tADH tADS tADH tADS t OEHZ tADVH tADVS...

Страница 24: ...is initiated by ADSP or ADSC 25 GW is HIGH Timing Diagrams continued tCYC t CL CLK tADH tADS ADDRESS t CH tAH tAS A2 tCEH tCES Single WRITE D A3 A3 A4 BURST READ Back to Back READs High Z Q A2 Q A4 Q...

Страница 25: ...d when entering ZZ mode See Cycle Descriptions table for all possible signal conditions to deselect the device 27 DQs are in high Z when exiting ZZ sleep mode Timing Diagrams continued t ZZ I SUPPLY C...

Страница 26: ...rid Array 14 x 22 x 2 4 mm Lead Free CY7C1363C 133BGXC CY7C1361C 133BZC 51 85180 165 ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm CY7C1363C 133BZC CY7C1361C 133BZXC 51 85180 165 ball Fine Pitch Ba...

Страница 27: ...20 x 1 4 mm Lead Free 3 Chip Enable lndustrial CY7C1363C 100AXI CY7C1361C 100AJXI 51 85050 100 pin Thin Quad Flat Pack 14 x 20 x 1 4 mm Lead Free 2 Chip Enable CY7C1363C 100AJXI CY7C1361C 100BGI 51 85...

Страница 28: ...IMENSIONS IN MILLIMETERS BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH 0 30 0 08 0 65 20 00 0 10 22 00 0 20 1 40 0 05 12 1 1 60 MAX 0 05 MIN 0 60 0 15 0 MIN 0 25 0 7 8X STAN...

Страница 29: ...K J U P N M T R 12 00 19 50 30 TYP 2 40 MAX A1 CORNER 0 70 REF U T R P N M L K J H G F E D C A B 2 1 4 3 6 5 7 1 00 3X REF 7 62 22 00 0 20 14 00 0 20 1 27 60 0 10 C 0 15 C B A 0 15 4X 0 05 M C 0 75 0...

Страница 30: ...tion PowerPC is a trademark of IBM Corporation All product and company names mentioned in this document are the trademarks of their respective holders Package Diagrams continued A 1 PIN 1 CORNER 15 00...

Страница 31: ...Jc for TQFP Package from 25 and 9 C W to 29 41 and 6 13 C W respectively Changed JA and Jc for BGA Package from 25 and 6 C W to 34 1 and 14 0 C W respectively Changed JA and Jc for FBGA Package from...

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