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CY7C1361C
CY7C1363C

Document #: 38-05541 Rev. *F

Page 12 of 31

IEEE 1149.1 Serial Boundary Scan (JTAG)

The CY7C1361C/CY7C1363C incorporates a serial boundary
scan test access port (TAP) in the BGA package only. The
TQFP package does not offer this functionality. This part
operates in accordance with IEEE Standard 1149.1-1900, but
doesn’t have the set of functions required for full 1149.1
compliance. These functions from the IEEE specification are
excluded because their inclusion places an added delay in the
critical speed path of the SRAM. Note the TAP controller
functions in a manner that does not conflict with the operation
of other devices using 1149.1 fully compliant TAPs. The TAP
operates using JEDEC-standard 3.3V or 2.5V I/O logic levels.

The CY7C1361C/CY7C1363C contains a TAP controller,
instruction register, boundary scan register, bypass register,
and ID register.

Disabling the JTAG Feature

It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied LOW
(V

) to prevent clocking of the device. TDI and TMS are inter-

nally pulled up and may be unconnected. They may alternately
be connected to V

through a pull-up resistor. TDO should be

left unconnected. Upon power-up, the device will come up in
a reset state which will not interfere with the operation of the
device.

TAP Controller State Diagram

The 0/1 next to each state represents the value of TMS at the
rising edge of TCK.

Test Access Port (TAP)

Test Clock (TCK)

The test clock is used only with the TAP controller. All inputs
are captured on the rising edge of TCK. All outputs are driven
from the falling edge of TCK.

Test MODE SELECT (TMS)

The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. It is allowable to
leave this ball unconnected if the TAP is not used. The ball is
pulled up internally, resulting in a logic HIGH level.

Test Data-In (TDI)

The TDI ball is used to serially input information into the
registers and can be connected to the input of any of the
registers. The register between TDI and TDO is chosen by the
instruction that is loaded into the TAP instruction register. TDI
is internally pulled up and can be unconnected if the TAP is
unused in an application. TDI is connected to the most signif-
icant bit (MSB) of any register. (See Tap Controller Block
Diagram.)

Test Data-Out (TDO)

The TDO output ball is used to serially clock data-out from the
registers. The output is active depending upon the current
state of the TAP state machine. The output changes on the
falling edge of TCK. TDO is connected to the least significant
bit (LSB) of any register. (See Tap Controller State Diagram.)

TAP Controller Block Diagram

Performing a TAP Reset

A RESET is performed by forcing TMS HIGH (V

) for five

rising edges of TCK. This RESET does not affect the operation
of the SRAM and may be performed while the SRAM is
operating.

At power-up, the TAP is reset internally to ensure that TDO
comes up in a High-Z state.

TAP Registers

Registers are connected between the TDI and TDO balls and
allow data to be scanned into and out of the SRAM test
circuitry. Only one register can be selected at a time through
the instruction register. Data is serially loaded into the TDI ball
on the rising edge of TCK. Data is output on the TDO ball on
the falling edge of TCK.

Instruction Register

Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the

TEST-LOGIC

RESET

RUN-TEST/

IDLE

SELECT

DR-SCAN

SELECT

IR-SCAN

CAPTURE-DR

SHIFT-DR