4-Mbit (128K x 32) Pipelined Sync SRAM
CY7C1339G
Cypress Semiconductor Corporation
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Document #: 38-05520 Rev. *F
Revised July 5, 2006
Features
• Registered inputs and outputs for pipelined operation
• 128K × 32 common I/O architecture
• 3.3V core power supply (V
DD
)
• 2.5V/3.3V I/O power supply (V
DDQ
)
• Fast clock-to-output times
— 2.6 ns (for 250-MHz device)
• Provide high-performance 3-1-1-1 access rate
• User-selectable burst counter supporting Intel
®
Pentium
®
interleaved or linear burst sequences
• Separate processor and controller address strobes
• Synchronous self-timed writes
• Asynchronous output enable
• Available in lead-free 100-Pin TQFP package, lead-free
and non-lead-free 119-Ball BGA package
• “ZZ” Sleep Mode Option
Functional Description
[1]
The CY7C1339G SRAM integrates 128K x 32 SRAM cells with
advanced synchronous peripheral circuitry and a two-bit
counter for internal burst operation. All synchronous inputs are
gated by registers controlled by a positive-edge-triggered
Clock Input (CLK). The synchronous inputs include all
addresses, all data inputs, address-pipelining Chip Enable
(CE
1
), depth-expansion Chip Enables (CE
2
and
CE
3
), Burst
Control inputs (ADSC, ADSP, and ADV), Write Enables
(BW
[A:D]
, and BWE), and Global Write (GW). Asynchronous
inputs include the Output Enable (OE) and the ZZ pin.
Addresses and chip enables are registered at rising edge of
clock when either Address Strobe Processor (ADSP) or
Address Strobe Controller (ADSC) are active. Subsequent
burst addresses can be internally generated as controlled by
the Advance pin (ADV).
Address, data inputs, and write controls are registered on-chip
to initiate a self-timed Write cycle.This part supports Byte Write
operations (see Pin Descriptions and Truth Table for further
details). Write cycles can be one to four bytes wide as
controlled by the byte write control inputs. GW when active
LOW causes all bytes to be written.
The CY7C1339G operates from a +3.3V core power supply
while all outputs may operate with either a +2.5 or +3.3V
supply. All inputs and outputs are JEDEC-standard
JESD8-5-compatible.
1
Note:
1. For best-practices recommendations, please refer to the Cypress application note
System Design Guidelines
on www.cypress.com.
A DDRESS
REGISTER
A DV
CLK
BURST
COUNTER
A ND
LOGIC
CLR
Q1
Q0
A DSP
A DSC
M ODE
BW E
GW
CE
1
CE
2
CE
3
OE
ENA BLE
REGISTER
OUTPUT
REGISTERS
SENSE
A M PS
OUTPUT
BUFFERS
E
PIPELINED
ENA BLE
INPUT
REGISTERS
A 0, A 1, A
BW
B
BW
C
BW
D
BW
A
M EM ORY
A RRA Y
D Q s
SLEEP
CONTROL
ZZ
A
[1:0]
2
DQ
A
BY TE
W RITE REGISTER
DQ
B
BY TE
W RITE REGISTER
DQ
C
BY TE
W RITE REGISTER
DQ
D
BY TE
W RITE REGISTER
DQ
A
BY TE
W RITE DRIVER
DQ
B
BY TE
W RITE DRIVER
DQ
C
BY TE
W RITE DRIVER
DQ
D
BY TE
W RITE DRIVER
Logic Block Diagram
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