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PRELIMINARY

CY7C1336H

Document #: 001-00210 Rev. *A

Page 14 of 15

© Cypress Semiconductor Corporation, 2006. The information contained herein is subject  to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Pentium is a registered trademark, and i486 is a trademark, of Intel Corporation. All product and company names mentioned in
this document may be the trademarks of their respective holders.

Ordering Information

Speed

(MHz)

Ordering Code

Package
Diagram

Package Type

Operating

Range

133

CY7C1336H-133AXC

51-85050

100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free

Commercial

CY7C1336H-133AXI

51-85050

100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free

Industrial

100

CY7C1336H-100AXC

51-85050

100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free

Commercial

CY7C1336H-100AXI

51-85050

100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free

Industrial

 Please contact your local Cypress sales representative for availability of these parts.

Package Diagram

NOTE:

1. JEDEC STD REF MS-026

2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH

MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE

3. DIMENSIONS IN MILLIMETERS

BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH

0.30±0.08

0.65

20.00±0.10

22.00±0.20

1.40±0.05

12°±1°

1.60 MAX.

0.05 MIN.

0.60±0.15

0° MIN.

0.25

0°-7°

(8X)

STAND-OFF

R 0.08 MIN.

TYP.

0.20 MAX.

0.15 MAX.

0.20 MAX.

R 0.08 MIN.

0.20 MAX.

14.00±0.10

16.00±0.20

0.10

SEE DETAIL

A

DETAIL

A

1

100

30

31

50

51

80

81

GAUGE PLANE

1.00 REF.

0.20 MIN.

SEATING PLANE

100-pin TQFP (14 x 20 x 1.4 mm) (51-85050)

51-85050-*B

[+] Feedback 

Содержание CY7C1336H

Страница 1: ...ADSP and ADV Write Enables BW A D and BWE and Global Write GW Asynchronous inputs include the Output Enable OE and the ZZ pin The CY7C1336H allows either interleaved or linear burst sequences selecte...

Страница 2: ...DQA VSSQ VDDQ DQA DQA NC NC DQC DQC VDDQ VSSQ DQC DQC DQC DQC VSSQ VDDQ DQC DQC NC VDD NC VSS DQD DQD VDDQ VSSQ DQD DQD DQD DQD VSSQ VDDQ DQD DQD NC A A CE1 CE 2 BW D BW C BW B BW A CE 3 V DD V SS CL...

Страница 3: ...merging from a deselected state ADV Input Synchronous Advance Input signal sampled on the rising edge of CLK When asserted it automatically incre ments the address in a burst cycle ADSP Input Synchron...

Страница 4: ...ing Byte Writes BWA controls DQA and BWB controls DQB BWC controls DQC and BWD controls DQD All I Os are tri stated during a Byte Write Since this is a common I O device the asynchronous OE input sign...

Страница 5: ...ontinue Burst Next H X X L X H L H L L H Q Read Cycle Continue Burst Next H X X L X H L H H L H Tri State Write Cycle Continue Burst Next X X X L H H L L X L H D Write Cycle Continue Burst Next H X X...

Страница 6: ...L H L H H Write Bytes C A DQPC DQPA H L H L H L Write Bytes C B DQPC DQPB H L H L L H Write Bytes C B A DQPC DQPB DQPA H L H L L L Write Byte D DQPD H L L H H H Write Bytes D A DQPD DQPA H L L H H L W...

Страница 7: ...0 3 0 8 V IX Input Leakage Current except ZZ and MODE GND VI VDDQ 5 5 A Input Current of MODE Input VSS 30 A Input VDD 5 A Input Current of ZZ Input VSS 5 A Input VDD 30 A IOZ Output Leakage Current G...

Страница 8: ...ns 100 TQFP Package Unit JA Thermal Resistance Junction to Ambient Test conditions follow standard test methods and procedures for measuring thermal impedance per EIA JESD51 30 32 C W JC Thermal Resis...

Страница 9: ...after CLK Rise 0 5 0 5 ns tADH ADSP ADSC Hold after CLK Rise 0 5 0 5 ns tWEH GW BWE BW A D Hold after CLK Rise 0 5 0 5 ns tADVH ADV Hold after CLK Rise 0 5 0 5 ns tDH Data Input Hold after CLK Rise 0...

Страница 10: ...IGH or CE2 is LOW or CE3 is HIGH tCYC tCL CLK tADH tADS ADDRESS t CH tAH tAS A1 tCEH tCES Data Out Q High Z tCLZ tDOH tCDV tOEHZ tCDV Single READ BURST READ tOEV tOELZ tCHZ Burst wraps around to its i...

Страница 11: ...S ADDRESS t CH tAH tAS A1 tCEH tCES High Z BURST READ BURST WRITE D A2 D A2 1 D A2 1 D A1 D A3 D A3 1 D A3 2 D A2 3 A2 A3 Extended BURST WRITE D A2 2 Single WRITE tADH tADS tADH tADS t OEHZ tADVH tADV...

Страница 12: ...ADV cycle is performed 19 GW is HIGH Timing Diagrams continued tCYC t CL CLK tADH tADS ADDRESS t CH tAH tAS A2 tCEH tCES Single WRITE D A3 A3 A4 BURST READ Back to Back READs High Z Q A2 Q A4 Q A4 1 Q...

Страница 13: ...ed when entering ZZ mode See Cycle Descriptions table for all possible signal conditions to deselect the device 21 DQs are in High Z when exiting ZZ sleep mode Timing Diagrams continued t ZZ I SUPPLY...

Страница 14: ...any names mentioned in this document may be the trademarks of their respective holders Ordering Information Speed MHz Ordering Code Package Diagram Package Type Operating Range 133 CY7C1336H 133AXC 51...

Страница 15: ...t A 428408 See ECN NXR Changed address of Cypress Semiconductor Corporation on Page 1 from 3901 North First Street to 198 Champion Court Changed Three State to Tri State Modified Input Load to Input L...

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