Cypress Semiconductor CY7C1305BV25 Скачать руководство пользователя страница 17 | Manualshive

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CY7C1307BV25

CY7C1305BV25

Document #: 38-05630 Rev. *A

Page 17 of 21

Capacitance

[22]

Parameter

Description

Test Conditions

Max.

Unit

C

IN

Input

Capacitance

T

A

= 25°C, f = 1 MHz,

V

DD

= 2.5V.

V

DDQ

= 1.5V

5

pF

C

CLK

Clock Input Capacitance

6

pF

C

O

Output Capacitance

7

pF

AC Test Loads and Waveforms

1.25V

0.25V

R = 50

Ω

5 pF

ALL INPUT PULSES

Device

R

L

= 50

Ω

Z

0

= 50

Ω

V

REF

= 0.75V

V

REF

= 0.75V

[23]

0.75V

Under
Test

0.75V

Device
Under
Test

OUTPUT

0.75V

V

REF

V

REF

OUTPUT

ZQ

ZQ

(a)

Slew Rate = 2 V/ns

RQ =
250

Ω

(b)

RQ =
250

Ω

[+] Feedback

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Содержание CY7C1305BV25

Страница 1: ...onsists of two separate ports to access the memory array The Read port has dedicated Data Outputs to support Read operations and the Write Port has dedicated Data Inputs to support Write operations QD...

Страница 2: ...Reg 36 18 18 72 18 BWS 0 1 Vref Write Add Decode Write Reg 36 A 17 0 18 C C 256Kx18 Array 256Kx18 Array 256Kx18 Array Write Reg Write Reg Write Reg 18 Logic Block Diagram CY7C1307BV25 128K x 36 Array...

Страница 3: ...16 VSS VSS VSS VSS VSS NC Q1 D2 N NC D17 Q16 VSS A A A VSS NC NC D1 P NC NC Q17 A A C A A NC D0 Q0 R TDO TCK A A A C A A A TMS TDI CY7C1307BV25 512K x 36 1 2 3 4 5 6 7 8 9 10 11 A NC GND 288M NC 72M W...

Страница 4: ...ns or K and K when in single clock mode When the Read port is deselected Q x 0 are automatically three stated CY7C1305BV25 Q 17 0 CY7C1307BV25 Q 35 0 RPS Input Synchronous Read Port Select active LOW...

Страница 5: ...d takes 2 clock cycles to complete Therefore Read accesses to the device can not be initiated on two consecutive K clock rises The internal logic of the device will ignore the second Read request Read...

Страница 6: ...t the same time the SRAM will deliver the most recent infor mation associated with the specified address location This includes forwarding data from a Write cycle that was initiated on the previous K...

Страница 7: ...he upper byte D 17 9 is written into the device D 8 0 will remain unaltered H H L H No data is written into the device during this portion of a Write operation H H L H No data is written into the devi...

Страница 8: ...D 8 0 and D 35 18 will remain unaltered H L H H L H During the Data portion of a Write sequence only the byte D 17 9 is written into the device D 8 0 and D 35 18 will remain unaltered H H L H L H Dur...

Страница 9: ...tween the TDI and TDO pins as shown in TAP Controller Block Diagram Upon power up the instruction register is loaded with the IDCODE instruction It is also loaded with the IDCODE instruction if the co...

Страница 10: ...e TDI and TDO pins PRELOAD allows an initial data pattern to be placed at the latched parallel outputs of the boundary scan register cells prior to the selection of another boundary scan test operatio...

Страница 11: ...to each state represents the value at TMS at the rising edge of TCK TEST LOGIC RESET TEST LOGIC IDLE SELECT DR SCAN CAPTURE DR SHIFT DR EXIT1 DR PAUSE DR EXIT2 DR UPDATE DR SELECT IR SCAN CAPTURE IR S...

Страница 12: ...CK Clock HIGH 20 ns tTL TCK Clock LOW 20 ns Set up Times tTMSS TMS Set up to TCK Clock Rise 10 ns tTDIS TDI Set up to TCK Clock Rise 10 ns tCS Capture Set up to TCK Rise 10 ns Hold Times tTMSH TMS Hol...

Страница 13: ...s Device ID 28 12 01011010011010101 01011010011100101 Defines the type of SRAM Cypress JEDEC ID 11 1 00000110100 00000110100 Allows unique identification of SRAM vendor ID Register Presence 0 1 1 Indi...

Страница 14: ...010 Captures the Input Output contents Places the boundary scan register between TDI and TDO Forces all SRAM output drivers to a High Z state RESERVED 011 Do Not Use This instruction is reserved for...

Страница 15: ...11E 61 4B 88 1K 8 9R 35 10E 62 3A 89 2L 9 11P 36 10D 63 1H 90 3L 10 10P 37 9E 64 1A 91 1M 11 10N 38 10C 65 2B 92 1L 12 9P 39 11D 66 3B 93 3N 13 10M 40 9C 67 1C 94 3M 14 11N 41 9D 68 1B 95 1N 15 9M 42...

Страница 16: ...OZ Output Leakage Current GND VI VDDQ Output Disabled 5 5 A VREF Input Reference Voltage 21 Typical value 0 75V 0 68 0 75 0 95 V IDD VDD Operating Supply VDD Max IOUT 0 mA f fMAX 1 tCYC 400 mA ISB1 Au...

Страница 17: ...citance TA 25 C f 1 MHz VDD 2 5V VDDQ 1 5V 5 pF CCLK Clock Input Capacitance 6 pF CO Output Capacitance 7 pF AC Test Loads and Waveforms 1 25V 0 25V R 50 5 pF ALL INPUT PULSES Device RL 50 Z0 50 VREF...

Страница 18: ...ise RPS WPS BWS0 BWS1 0 7 ns tHD tHD D x 0 Hold after Clock K and K Rise 0 7 ns Output Times tCO tCHQV C C Clock Rise or K K in single clock mode to Data Valid 25 2 5 ns tDOH tCHQX Data Output Hold af...

Страница 19: ...after a NOP 29 In this example if address A2 A1 then data Q20 D10 and Q21 D11 Write data is forwarded immediately as read results This note applies to the whole diagram K 1 2 3 4 5 6 7 K RPS WPS A Q...

Страница 20: ...eed MHz Ordering Code Package Diagram Package Type Operating Range 167 CY7C1305BV25 167BZC 51 85180 165 ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm Commercial CY7C1307BV25 167BZC CY7C1305BV25 167...

Страница 21: ...ription Table Changed tTCYC from 100 ns to 50 ns changed tTF from 10 MHz to 20 MHz and changed tTH and tTL from 40 ns to 20 ns in TAP AC Switching Characteristics table Modified the ZQ pin definition...

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