CY7C1041DV33
Document #: 38-05473 Rev. *E
Page 7 of 13
Figure 5. Read Cycle No. 2 (OE Controlled)
[17, 18]
Figure 6. Write Cycle No. 1 (CE Controlled)
[19, 20]
Switching Waveforms
(continued)
50%
50%
DATA VALID
t
RC
t
ACE
t
DOE
t
LZOE
t
LZCE
t
PU
HIGH IMPEDANCE
t
HZOE
t
HZBE
t
PD
HIGH
OE
CE
ICC
ISB
IMPEDANCE
ADDRESS
DATA OUT
V
CC
SUPPLY
t
DBE
t
LZBE
t
HZCE
BHE, BLE
CURRENT
I
CC
I
SB
t
HD
t
SD
t
SCE
t
SA
t
HA
t
AW
t
PWE
t
WC
BW
DATAIO
ADDRESS
CE
WE
BHE, BLE
t
Notes
18. Address valid prior to or coincident with CE transition LOW.
19. Data IO is high impedance if OE or BHE and BLE = V
IH.
20. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high impedance state.
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