CY7C1024DV33
Document Number: 001-08353 Rev. *C
Page 6 of 9
Switching Waveforms
Figure 3. Read Cycle No. 1 (Address Transition Controlled)
[13, 14]
Figure 4. Read Cycle No. 2 (OE Controlled)
[3, 14, 15]
Figure 5. Write Cycle No. 1 (CE Controlled)
[3, 16, 17]
PREVIOUS DATA VALID
DATA VALID
RC
t
AA
t
OHA
t
RC
ADDRESS
DATA OUT
50%
50%
DATA VALID
t
RC
t
ACE
t
DOE
t
LZOE
t
LZCE
t
PU
HIGH IMPEDANCE
t
HZOE
t
HZCE
t
PD
HIGH
ICC
ISB
IMPEDANCE
OE
CE
ADDRESS
DATA OUT
V
CC
SUPPLY
CURRENT
t
WC
DATA VALID
t
AW
t
SA
t
PWE
t
HA
t
HD
t
SD
t
SCE
t
SCE
CE
WE
DATA I/O
ADDRESS
Notes
13. Device is continuously selected. OE, CE = V
IL
.
14. WE is HIGH for read cycle.
15. Address valid before or similar to CE transition LOW.
16. Data I/O is high impedance if OE = V
IH
.
17. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high impedance state.
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